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Instructions & addressing formulas

Instruction sets and addressing modes. 5 formulas for GATE CS Computer Organization and Architecture, each with when to use it. Each is explained in the topic notes.

All 5 Instructions & addressing formulas

BITS NEEDED TO ENCODE N DISTINCT ITEMS

Smallest with . Applies to an opcode field ( instructions), a register field ( registers) or an address field ( addressable locations).

EXPANDING OPCODES: W-BIT INSTRUCTIONS, A-BIT ADDRESS FIELDS

, , are the numbers of two-, one- and zero-address instructions. The two-address format has a -bit opcode; each unused two-address code gives one-address codes, and each unused one-address code gives zero-address codes. Assumes every instruction is exactly bits, every address field is bits, and .

DISPLACEMENT-TYPE ADDRESSING

is the index register (indexed), the base register (base) or the PC (PC-relative); is the displacement field. For PC-relative, is signed.

PC-RELATIVE BRANCH TARGET

is the address of the instruction AFTER the branch (branch address + branch length), unless a question says the branch's own address is used. is the signed displacement in bytes, unless the ISA scales it.

RANGE OF AN N-BIT TWO'S-COMPLEMENT DISPLACEMENT

Range in displacement units relative to the base PC. If the displacement counts instructions of bytes, multiply by to get the byte range.

Where this was asked: 2018 (2), 2020 (1), 2023 (1), 2024 (2), 2025 (2), 2026 (3). See the 11 previous-year questions on Instructions & addressing. This shows what was asked, not what will be asked.