IAE Academy

GATE 2023 CS Q.42: solution and answer

GATE 2023 · CSQ.42 · 2 marks · MCQ

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

GATE 2023 CS question 42: 12 address lines IA11 (MSB) down to IA0 (LSB) enter from the left.Tap to open full size
Figure from the GATE 2023 CS paper. It is part of the question.
Figure description

12 address lines IA11 (MSB) down to IA0 (LSB) enter from the left. The upper 10 lines actually used for addressing (all lines except IA4 and IA3) are bundled as a 10-bit bus labelled '10-bit' and fed to the 'Addr' input port of each of four 1KB memory blocks, labelled (left to right) with data-output/name X1, X2, X3, X4, each also having a CS (chip select) pin. IA4 and IA3 are instead routed down into a 2-to-4 decoder block: inputs A1 = IA4, A0 = IA3; outputs Q0, Q1, Q2, Q3 (top to bottom). Q0 connects to the CS of the first (X1) memory block, Q1 to the CS of the second (X2) block, Q2 to the CS of the third (X3) block, and Q3 to the CS of the fourth (X4) block, each via a horizontal wire running across to that block's CS pin. CS is active-high.

  1. (A)

    (0, 1, 2, 3)

  2. (B)

    (0, 1024, 2048, 3072)

  3. (C)

    (0, 8, 16, 24)

  4. (D)

    (0, 0, 0, 0)

Answer and solution

ANSWER

The correct answer is option (C): (X1, X2, X3, X4) = (0, 8, 16, 24).

Official answer: CSource: Official answer key, GATE 2023 CS (IIT Kanpur)

  1. Total memory = 4KB = 2^12 bytes, so 12 address lines IA11–IA0 are needed, matching the given lines.

  2. Each 1KB block needs 10 address bits for its Addr port (2^10 = 1024 bytes). The figure shows exactly 10 of the 12 lines — all except IA4 and IA3 — feeding the Addr port of every block in parallel.

  3. IA4 and IA3 are bits 4 and 3 of the address (not the MSBs). They instead feed the 2-to-4 decoder as A1=IA4, A0=IA3, whose outputs Q0..Q3 chip-select X1..X4 respectively.

  4. At a block's starting location (Addr=0), all 10 bits that feed the Addr port (bits 11,10,9,8,7,6,5,2,1,0) are 0 by definition.

  5. X1 selected when Q0 is active, i.e. IA4 IA3 = 00 ⇒ bit4=0, bit3=0. With all other bits 0, the 12-bit address IA11..IA0 = 0 ⇒ decimal 0.

  6. X2 selected when Q1 is active, i.e. IA4 IA3 = 01 ⇒ bit4=0, bit3=1, all other bits 0 ⇒ address = .

  7. X3 selected when Q2 is active, i.e. IA4 IA3 = 10 ⇒ bit4=1, bit3=0, all other bits 0 ⇒ address = .

  8. X4 selected when Q3 is active, i.e. IA4 IA3 = 11 ⇒ bit4=1, bit3=1, all other bits 0 ⇒ address = .

  9. So (X1,X2,X3,X4) = (0, 8, 16, 24), matching option (C).

KEY IDEA

The 10-bit Addr port of every block is fed by all address lines EXCEPT IA4 and IA3, which instead go to a 2-to-4 decoder that generates the chip-select for each block. So "starting location" (Addr port = 0) only forces the ten bus bits to 0; IA4 and IA3 are free to vary block-to-block since they only pick which block is selected — and their contribution to the 12-bit address is and , not the top two (MSB) bits.

WATCH OUT FOR

Assuming the two lines going to the decoder must be the two MSBs (IA11, IA10), which would wrongly give offsets in multiples of 1024 (option B) — or assuming a decoder always implies a simple linear block order 0,1,2,3 (option A). The trap is that IA4 and IA3 sit in the middle of the address, not at either end, so their weight is and .

From the GATE 2023 CS paper. Every question of this paper · Download the full paper · All 22 Memory & cache questions, with notes

More Memory & cache questions