Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.
For a given memory reference, which of the following sequences of events can NEVER happen?
- (A)
TLB miss, Page table hit, Cache hit
- (B)
TLB hit, Page table miss, Cache hit
- (C)
TLB miss, Page table miss, Cache hit
- (D)
TLB miss, Page table miss, Cache miss
