Logic families formulas

Uses worst-case values: the minimum $V_{OH}$ and the minimum $V_{IH}$.

Uses worst-case values: the maximum $V_{IL}$ and the maximum $V_{OL}$. The family's noise margin is the smaller of $N{M}_H$ and $N{M}_L$.

All currents are magnitudes. Round each ratio down, then take the smaller. A CMOS input draws almost no DC current, so CMOS fan-out is limited by load capacitance (it slows the gate), not by this formula.

$t_{PHL}$ is the time from the 50% point of the input edge to the 50% point of the output's HIGH-to-LOW edge. $t_{PLH}$ is the same for the output's LOW-to-HIGH edge. Rise and fall times are measured from 10% to 90%. If a question asks for the worst-case delay, use $\max (t_{PHL},t_{PLH})$ instead.

Assumes the output spends equal time HIGH and LOW (50% duty cycle). $I_{CCH}$ and $I_{CCL}$ are the supply currents of one gate with its output HIGH and LOW. If a datasheet gives them for a whole package, divide by the number of gates in the package.

The energy per switching event. It is a figure of merit, and lower is better. Units: mW times ns gives pJ.

$V_M$ is the input voltage at which $V_{out}=V_{in}$. It comes from equating the two saturation currents (square law, $\lambda =0$). A stronger NMOS (larger $k_n$) pulls $V_M$ down, and a stronger PMOS pushes it up.

When this holds and $V_{Tn}=|V_{Tp}|$, $V_M=V_{DD}/2$, and the pull-up and pull-down strengths are equal.

Valid only for a symmetric inverter ($k_n=k_p$, $V_{Tn}=|V_{Tp}|=V_T$, square law). $V_{IL}$ and $V_{IH}$ are the two points where the slope of the VTC is $-1$. Note $V_{IL}+V_{IH}=V_{DD}$.

Assumes a step input. $R_n$ and $R_p$ are the effective on-resistances of the pull-down and pull-up paths (a series stack adds its resistances), and $C_L$ is the load capacitance. The factor 0.69 is $\ln 2$, the time to reach the 50% point.

Assumes a full-swing output. Half of this energy is dissipated in the pull-up at once. The other half is stored on $C_L$ and dissipated in the pull-down at the next 1-to-0 transition.

$f$ is the rate at which the output completes full LOW-HIGH-LOW cycles. For example, an inverter driven by a clock of frequency $f$ has an output that completes one full cycle per clock period. Assumes the output swings fully between the rails each time. The transistors' W/L and on-resistance do not appear, except through their own capacitance included in $C_L$.

Convention used here: $\alpha$ is the probability that the node makes a 0-to-1 transition in a given clock cycle. A clock node has $\alpha =1$. A node that changes state on every clock cycle has $\alpha =0.5$, because it rises only on every second cycle. For $N$ similar gates, multiply by $N$. Some questions instead define $\alpha$ as the probability of a transition in either direction per cycle; with that definition $P_{dyn}=\frac{1}{2}\alpha C_L{V}_{DD}^2{f}_{clk}$. Use the definition the question gives.

In $G$, series NMOS form a product and parallel NMOS form a sum. A single static CMOS stage can only realise an inverting (negative-unate) function: one that can be written with every input appearing only in complemented form. A function such as AND, OR or XOR needs extra inverters.

Each appearance of an input (a literal) in the form of $G$ you build needs one NMOS and one PMOS, so factoring $G$ saves transistors: $AB+AC$ needs 8, but $A(B+C)$ needs 6. Add 2 transistors for every inverter, whether it complements an input or inverts the output.