Sequential formulas

$t_p$ = width of the HIGH clock pulse, $t_{pd}$ = flip-flop propagation delay, $T$ = clock period. Applies to a level-triggered JK flip-flop in toggle mode ($J=K=1$).

The constraint $SR=0$ is part of the equation, because $S=R=1$ is not allowed. $SR=00$ holds, $10$ sets, $01$ resets.

$JK=00$ holds, $01$ resets, $10$ sets, $11$ toggles. No input combination is forbidden.

The next state is the value of $D$ at the active edge, so a D flip-flop delays its input by one clock period.

$T=1$ toggles, $T=0$ holds. In toggle mode the output frequency is half the clock frequency, and n toggling stages in cascade divide the clock by $2^n$.

Applies to a mod-N counter and to an N-state machine with binary state encoding. The $2^n-N$ unused states must be checked for lock-out.

$f_{\text{out}}$ is the rate at which the whole state repeats. In a binary mod-N counter it is also the frequency of the most significant output. Lower bits can repeat faster: in a mod-6 binary counter (0 to 5), $Q_0$ still alternates 0, 1 on every clock, so its frequency is $f_{clk}/2$. The output need not have a 50% duty cycle; in a mod-5 binary counter the MSB is HIGH for 1 clock period in 5. A mod-M counter cascaded into a mod-N counter gives a mod-$MN$ counter with $f_{\text{out}}=f_{clk}/(MN)$. In a full n-bit binary (mod-$2^n$) counter, bit $Q_k$ ($k=0$ for the LSB) has frequency $f_{clk}/2^{k+1}$ and a 50% duty cycle.

The worst case is a transition in which all n stages change (for example 0111 to 1000 in a 4-bit up counter), which takes $n{t}_{pd}$. The clock period must be at least this long for the count to settle, and be readable, before the next edge. If a decoder must also read the count, add its delay or strobe time $t_s$: $f_{\text{max}}=1/(n{t}_{pd}+t_s)$.

This is the up counter. Down counter: $T_k=\overline{Q_0}\overline{Q_1}\cdots \overline{Q_{k-1}}$. Up/down with mode input $M$ (1 = up, 0 = down): $T_k=M{Q}_0\cdots Q_{k-1}+\overline{M}\overline{Q_0}\cdots \overline{Q_{k-1}}$. With JK flip-flops, use $J_k=K_k=T_k$.

$0.693\approx \ln 2$: an RC charge toward $V_{CC}$ from $V_{CC}/3$ to $2V_{CC}/3$, or a discharge toward 0 from $2V_{CC}/3$ to $V_{CC}/3$, takes $RC\ln 2$. Duty cycle $=t_H/(t_H+t_L)=(R_A+R_B)/(R_A+2R_B)$, which is always above 50% in this basic circuit. Applies to the standard astable connection with the control pin unused.

$C$ charges from 0 toward $V_{CC}$, and the output falls when $C$ reaches $2V_{CC}/3$. So $t_w=RC\ln \left(V_{CC}/(V_{CC}-2V_{CC}/3)\right)=RC\ln 3$. Applies with the control pin unused.

Each output is HIGH for one clock period in every n (duty cycle $1/n$). It is not self-starting without extra logic: from 0000, or from a state with two 1s, it never reaches the intended cycle.

Each output is a square wave with a 50% duty cycle. It is not self-starting without extra logic. In a 3-bit Johnson counter, for example, the unused states 010 and 101 switch back and forth between each other forever.

Valid for both overlapping and non-overlapping detection. The states record how many pattern bits have been matched (0 to $L-1$), and a Moore machine needs one extra state whose output is 1. Minimum flip-flops = $\lceil {\log }_{2}S\rceil$.

Follows from the setup constraint $T\ge t_{\text{cq}}+t_{\text{comb,max}}+t_{su}$. Use the maximum clock-to-Q delay and the longest (critical) combinational path between any two flip-flops. Applies to synchronous counters, registers and FSMs.

Uses the minimum (contamination) delays. The clock period does not appear, so slowing the clock cannot fix a hold violation. It is fixed by adding delay to the short path, or by using flip-flops with a shorter hold time or a longer minimum clock-to-Q delay.

Positive skew gives the data extra time and relaxes setup; negative skew tightens it.

Positive skew makes hold harder to meet; negative skew makes it easier. Skew therefore trades setup margin against hold margin.