Memory & cache formulas

The fraction of memory references satisfied directly by the cache. Miss ratio $=1-h$.

Use this when main memory is accessed only after the cache lookup has missed, so a miss costs $T_c+T_m$. $T_m$ is the time to get the needed data from main memory. If the question says a whole block is transferred into the cache on a miss and gives the block-transfer time, use that time as the miss cost in place of a single-word $T_m$.

Use this when the cache and main memory are looked up in parallel. On a miss, the cache-check time is hidden inside the longer memory access and is not added again.

The miss penalty is the EXTRA time a miss costs on top of the hit time. With hierarchical access and $T_{penalty}=T_m$, this is the same as the hierarchical formula above.

Number of lines $=$ cache size $÷$ block size, whatever the associativity. The extra bits per line are whatever the question specifies. Typically that is a valid bit, a dirty bit for a write-back cache, and any replacement bits.

Model: L2 is accessed only on an L1 miss, and main memory only on an L2 miss, with each lower-level time added on top (hierarchical). $M{R}_{L2}$ here is the LOCAL miss rate of L2: misses in L2 $÷$ accesses that reach L2 (the L1 misses). It is not the global miss rate.

The fraction of ALL CPU accesses that miss in both L1 and L2 and go to main memory. If a question gives a global L2 miss rate, divide it by $M{R}_{L1}$ to get the local rate before using the AMAT formula.

Here $M$ and $m$ are numbers of words, and $w$ and $b$ are bits per word. Each row places $w/b$ chips side by side to form the full word width. $M/m$ rows are stacked to supply all the words. The memory needs ${\log }_{2}M$ address lines. Each chip takes the low ${\log }_{2}m$ of them, and the remaining ${\log }_2(M/m)$ high-order bits drive a decoder that selects one row.

Model: all $n$ banks start their access together. The first word is on the bus after $T_{access}$ (the bank access time, including placing the word on the bus). Each further word, already read in its own bank, needs only one bus transfer time $T_{transfer}$. Questions may define the timing differently, for example with a separate address-send cycle. Use the question's model when it gives one.

Same model with a single bank: each word is a full, separate access. This is the baseline against which the speedup from interleaving is measured.

Seek: moving the head to the correct track. Rotational latency: waiting for the target sector to rotate under the head. Transfer: reading or writing the data once positioned. Add a controller overhead only if the question gives one. Unless stated otherwise, a given seek time is taken as the average seek time.

Half the time of one revolution, in seconds (RPM = revolutions per minute). This is the AVERAGE. The worst case is a full revolution and the best case is zero.

One track passes under the head per revolution, so the transfer rate is the track capacity times the revolutions per second. Equivalently, reading one sector takes (revolution time) $÷$ (sectors per track).