I/O, interrupts & DMA formulas

$n$ = number of interrupts serviced in the period analysed; $t_{cs}$ = context-save time; $t_{svc}$ = the ISR's own execution time, excluding save and restore; $t_{cr}$ = context-restore time. Divide by the total elapsed time to get the fraction of CPU time spent.

$t_{\text{int}}$ = total CPU time per interrupt (save + service + restore); $T_{\text{int}}$ = average time between interrupts; $r=1/T_{\text{int}}$ = interrupts per second. If there is one interrupt per word, $r$ is the device's word rate. This holds only while $t_{\text{int}}<T_{\text{int}}$. Otherwise the CPU cannot keep up and data is lost.

$N$ = number of words in the block; $t_{\text{mem}}$ = one memory (bus) cycle time. This holds when:

• each word needs exactly one memory cycle;
• the words are available back to back (for example from the device's buffer);
• the DMAC holds the bus for the whole block;
• bus request/grant overhead is ignored.

During this time the CPU cannot use the bus. It can still carry on with internal operations that need no bus.

One bus cycle is stolen per word, assuming each word needs exactly one memory access. The two sides are equal in the standard model, where the CPU would have used the bus in every stolen cycle and arbitration overhead is ignored. This is the same product as burst mode, but it means something different. In cycle stealing, the loss is spread as $N$ separate one-cycle delays, and the total elapsed time is set by the device's word rate. In burst mode, the CPU is locked out for one continuous stretch.

$t_c$ = time of the one bus cycle stolen per word; $T_w$ = time between successive word transfers, i.e. the device's word period. This assumes the CPU would otherwise use the bus in every cycle, and $t_c\le T_w$.

Some questions give a time $x$ to prepare a word and a time $y$ to transfer it ($y=t_c$). If the device cannot prepare the next word during the transfer, $T_w=x+y$. If preparation overlaps the transfer, $T_w=x$ (assuming $x\ge y$). State which reading you use.

$t_{\text{setup}}$ = CPU time to program the DMAC for one block; $t_{\text{done}}$ = CPU time for the completion interrupt. This assumes the device transfers continuously, one block after another, and ignores the bus cycles DMA steals. Add the stolen-cycle fraction separately if the question asks for it.