GATE CS

I/O interface

Interrupts and DMA

I/O interfacing bridges the speed gap between a fast CPU and much slower I/O devices. There are three transfer techniques: programmed I/O, interrupt-driven I/O and DMA. When several devices can interrupt, the CPU identifies and prioritises them by polling, vectored interrupts, a priority encoder or a daisy chain. A DMA controller moves whole blocks between a device and memory in burst, cycle-stealing or transparent mode, with no CPU instruction per word. The standard calculations are: the fraction of CPU time spent servicing interrupts, the time a burst DMA transfer takes, the fraction of bus cycles that cycle-stealing DMA takes from the CPU, and the CPU time spent setting up and finishing a DMA block.

8 previous-year questions · 8 solved · 6 practice questions

I/O Data Transfer Techniques: The Big Picture

A CPU is much faster than most I/O devices (keyboards, disks, network interfaces). So a computer needs a way to move data between memory and a device without wasting CPU time or losing data. There are three techniques. In order of decreasing CPU involvement per unit of data:

Programmed I/O: the CPU keeps testing the device's status flag itself (busy-waiting).
Interrupt-driven I/O: the CPU runs its own program and is interrupted only when the device is ready.
DMA (Direct Memory Access): a separate controller moves a whole block of data to or from memory, and the CPU runs no instruction for any individual word.

The numerical work on this topic comes down to a few calculations: the fraction of CPU time spent servicing interrupts, the time a DMA transfer takes, and the fraction of CPU time lost to DMA.

Technique	Who moves the data	CPU involvement per word	Suited to
Programmed I/O	The CPU, in a busy-wait loop	The CPU runs a status-check instruction repeatedly until the device is ready, then moves the word itself	Very simple systems, or when nothing else useful can run
Interrupt-driven I/O	The CPU, but only when notified	The CPU is interrupted once per word (or small unit), moves it, then goes back to other work	Low-to-moderate, irregular data rates (keyboard, mouse)
DMA	A dedicated DMA controller (DMAC)	The CPU runs a few set-up instructions once, runs no instruction per word, and receives one interrupt at the end of the whole block	Large blocks at high, sustained data rates (disk, network)

Interrupt-Driven I/O

In interrupt-driven I/O the CPU runs its own program and is free to do other work. When the device becomes ready, it asserts an interrupt request line.

If interrupts are enabled, the CPU first finishes the instruction it is currently executing. In the standard model it never stops partway through an instruction. It then transfers control to an interrupt service routine (ISR). The ISR moves the data, and the CPU resumes the interrupted program exactly where it left off.

Sequence of events on each interrupt (standard model)

The device becomes ready and asserts its interrupt request.
The CPU finishes the instruction in progress. It checks for interrupts only between instructions, and only if interrupts are enabled.
The CPU saves the context. On most processors the hardware saves the program counter (PC) and status flags automatically. Any other registers the ISR uses are saved by the ISR's first instructions.
The CPU transfers control to the ISR. The ISR address is either one fixed address (non-vectored) or an address supplied by the device (vectored).
The ISR moves one unit of data (for example one byte or one word) between the device and memory. It then acknowledges the device, which clears the request so that the same interrupt does not trigger again.
The ISR restores the registers it saved and executes a return-from-interrupt, which restores the PC and flags. The interrupted program resumes.

Terms to know

Maskable interrupt: can be disabled by clearing the CPU's interrupt-enable flag, or masked individually in a mask register. Non-maskable interrupt (NMI): cannot be disabled this way. It is used for critical events such as a power failure.
Many processors disable further maskable interrupts automatically when they enter an ISR. The ISR can re-enable them.
Nested interrupts: if an ISR re-enables interrupts, a higher-priority device can interrupt it. The CPU saves the ISR's context and services the higher-priority device first.
Hardware (external) interrupts come from devices and are asynchronous to the program. Software interrupts, traps and exceptions are caused by executing an instruction (for example a divide-by-zero or a system call), so they are synchronous to the program.

TOTAL INTERRUPT-SERVICING OVERHEAD FOR N INTERRUPTS

T_{ISR,total} = n (t_{cs} + t_{s v c} + t_{cr})

$n$ = number of interrupts serviced in the period analysed; $t_{cs}$ = context-save time; $t_{s v c}$ = the ISR's own execution time, excluding save and restore; $t_{cr}$ = context-restore time. Divide by the total elapsed time to get the fraction of CPU time spent.

FRACTION OF CPU TIME SPENT ON ONE DEVICE'S INTERRUPTS

f_{CPU} = \frac{t _{int}}{T _{int}} = r \times t_{int}

$t_{int}$ = total CPU time per interrupt (save + service + restore); $T_{int}$ = average time between interrupts; $r = 1/ T_{int}$ = interrupts per second. If there is one interrupt per word, $r$ is the device's word rate. This holds only while $t_{int} < T_{int}$ . Otherwise the CPU cannot keep up and data is lost.

A conceptual outline of interrupt-driven output, showing the save, transfer, acknowledge and restore sequence:

main program:
    enable_device_interrupts()
    do_other_work()                  // no status polling here

ISR_device:                          // entered after the current instruction completes
    save the registers the ISR uses  // PC and flags already saved by hardware
    DATA_REG = buffer[i]             // transfer exactly one unit
    i = i + 1
    acknowledge the device           // clears its request so it does not re-trigger
    restore the saved registers
    return from interrupt            // restores PC and flags

EXAM TIP

Interrupt-driven I/O pays for one full interrupt (save, service, restore) for every unit transferred. For a device with a high, steady data rate, that per-unit cost is what makes DMA the better choice: DMA needs one interrupt per block, not one per word.

Interrupt Handling: Vectored, Priority and Daisy-Chained Interrupts

When more than one device can interrupt, the CPU has to do two things:

1. Find out which device interrupted.
2. If several devices request at once, decide which one to service first.

There are four standard mechanisms for this.

The four mechanisms

Non-vectored (polled) interrupt: every interrupt makes the CPU jump to one fixed ISR address. That ISR then reads each device's status register in a fixed software order to find the source. The polling order is the priority order, so software sets it and it is easy to change.
Vectored interrupt: the interrupting device, or an interrupt controller acting for it, supplies an address or code (the vector). This usually happens on the data bus during an interrupt-acknowledge (INTACK) cycle. The vector points the CPU directly to that device's own ISR, so no polling is needed.
Parallel priority interrupt (priority encoder): each device's request line goes through a mask register into a hardware priority encoder. If several unmasked requests are active together, the encoder outputs the code of the highest-priority one only. That code forms the vector or part of it. Lower-priority requests stay pending. Which encoder input a device is wired to fixes its priority, and software can enable or disable individual lines through the mask register.
Daisy chaining (serial priority): the CPU's INTACK output is wired through the devices in series. A device with no pending request passes INTACK on to the next device. A device with a pending request stops INTACK from going further and places its vector on the data bus. The requesting device wired closest to the CPU therefore wins. Priority is fixed by wiring position, not by software.

Scheme	How the source is identified	Extra hardware needed	What fixes the priority order
Non-vectored (polling)	Software polls each device's status register in turn	None beyond a shared interrupt line	Software (the polling order), easy to change
Vectored	The device or interrupt controller supplies a vector, usually during an INTACK cycle	Logic in each device (or a controller) to place a vector on the data bus	A separate scheme (encoder or chain) that resolves simultaneous requests
Parallel priority (encoder)	The encoder outputs the code of the highest-priority unmasked request	Mask register plus priority encoder	Wiring to encoder inputs; the mask register can disable individual lines
Daisy chain (serial)	The first requesting device along the chain from the CPU blocks INTACK and supplies its vector	Only a serial INTACK connection through the devices	Physical position in the chain; the device closest to the CPU wins

EXAM TIP

Consequences of daisy chaining:

Priority can be changed only by rewiring.
A device near the CPU that requests often can starve devices further down the chain.
A faulty device that fails to pass INTACK on cuts off every device beyond it.

Direct Memory Access (DMA)

With DMA, a dedicated DMA controller (DMAC) moves an entire block of data directly between an I/O device and memory. The DMAC drives the address, data and control lines itself, and the CPU runs no instruction for any individual word of the block. The CPU's only jobs are to set up the transfer beforehand and to handle one interrupt when the whole block is done.

What the CPU programs into the DMAC before starting

The starting memory address, in the DMAC's address register.
The number of words to transfer, in the DMAC's word-count register.
The direction (device to memory, or memory to device) and the mode (burst, cycle stealing or transparent), in the DMAC's control register.
A start command. After this the CPU goes back to its own program.

Sequence of a DMA transfer

The CPU programs the DMAC (address, word count, direction, mode), issues a start command and resumes its own program.
When a word is ready (in burst mode, when the block is ready), the device signals the DMAC. The DMAC then requests the bus from the CPU (bus request, called HOLD on some processors).
The CPU finishes its current bus cycle. It does not need to finish the current instruction. It releases its bus lines and grants the bus (bus grant, called HLDA on some processors).
The DMAC puts the memory address on the address bus and issues the read/write control signals. The word moves directly between the device and memory. The DMAC then increments its address register and decrements its word count.
In cycle-stealing mode, the DMAC releases the bus after each word and repeats steps 2 to 4 for the next word. In burst mode, it keeps the bus and repeats step 4 until the word count reaches zero.
When the word count reaches zero, the DMAC releases the bus and raises one interrupt to tell the CPU the block is complete.

EXAM TIP

When the CPU responds: an interrupt is recognised only at the end of an instruction. A DMA bus request can be granted at the end of any bus (machine) cycle, which may be in the middle of an instruction. The DMAC only needs the bus, not the CPU's registers, so no context has to be saved.

BURST (BLOCK) MODE DMA TRANSFER TIME

T_{burst} = N \times t_{mem}

$N$ = number of words in the block; $t_{mem}$ = one memory (bus) cycle time. This holds when:

each word needs exactly one memory cycle;
the words are available back to back (for example from the device's buffer);
the DMAC holds the bus for the whole block;
bus request/grant overhead is ignored.

During this time the CPU cannot use the bus. It can still carry on with internal operations that need no bus.

DMA Transfer Modes and Their Timing

The DMA modes differ in when the DMAC takes the bus. That changes how fast the block finishes and how much the CPU's own program is slowed down.

Mode	When the DMAC holds the bus	Effect on the CPU's program	Time to finish the block
Burst (block)	Continuously, from the first word to the last	The CPU cannot use the bus for the whole block; it can do only internal operations	Fastest when words are available back to back
Cycle stealing	One bus cycle per word; releases the bus after each word and requests it again for the next	The CPU loses at most one bus cycle per word, and exactly one if it needed the bus in that cycle; it makes progress between steals	Later than burst when words are available back to back; when the device is the bottleneck, both modes finish at the device's pace
Transparent (hidden, interleaved)	Only in bus cycles the CPU is not using (for example internal ALU or register cycles)	No slowdown, in principle; needs extra logic to detect free cycles	Usually the slowest; depends on how many free bus cycles the CPU leaves

CPU TIME LOST TO CYCLE-STEALING DMA OVER N WORDS

T_{CPU,lost} \leq N \times t_{mem}

One bus cycle is stolen per word, assuming each word needs exactly one memory access. The two sides are equal in the standard model, where the CPU would have used the bus in every stolen cycle and arbitration overhead is ignored. This is the same product as burst mode, but it means something different. In cycle stealing, the loss is spread as $N$ separate one-cycle delays, and the total elapsed time is set by the device's word rate. In burst mode, the CPU is locked out for one continuous stretch.

FRACTION OF BUS CYCLES TAKEN BY CYCLE-STEALING DMA

f_{stolen} = \frac{t _{c}}{T _{w}}

$t_{c}$ = time of the one bus cycle stolen per word; $T_{w}$ = time between successive word transfers, i.e. the device's word period. This assumes the CPU would otherwise use the bus in every cycle, and $t_{c} \leq T_{w}$ .

Some questions give a time $x$ to prepare a word and a time $y$ to transfer it ( $y = t_{c}$ ). If the device cannot prepare the next word during the transfer, $T_{w} = x + y$ . If preparation overlaps the transfer, $T_{w} = x$ (assuming $x \geq y$ ). State which reading you use.

PERCENTAGE OF CPU TIME USED ON DMA SET-UP AND COMPLETION

%_{CPU} = \frac{t _{setup} + t _{done}}{T _{block}} \times 100, T_{block} = \frac{block size}{device data rate}

$t_{setup}$ = CPU time to program the DMAC for one block; $t_{done}$ = CPU time for the completion interrupt. This assumes the device transfers continuously, one block after another, and ignores the bus cycles DMA steals. Add the stolen-cycle fraction separately if the question asks for it.

Worked Examples and Exam Tips

WORKED EXAMPLE

A DMA controller transfers a block of 2000 words from a disk buffer to memory in burst mode. The memory cycle time is 100 ns, each word needs exactly one memory cycle, and the CPU cannot use the bus during the transfer. Ignore bus-arbitration overhead.

(a) Find the total transfer time.

(b) Suppose instead each word were moved by interrupt-driven I/O, with each interrupt (save + one-word transfer + restore) costing 1.5 µs of CPU time. Find the total CPU time spent on the block, and compare the CPU time the two methods consume. Ignore DMA set-up and the single completion interrupt.

Solution

(a) Burst mode: $T_{burst} = N \times t_{mem} = 2000 \times 100 ns = 200, 000 ns = 200 μ s$ . The CPU is locked out of the bus for these 200 µs.
(b) Interrupt-driven: one interrupt per word, so CPU time $= 2000 \times 1.5 μ s = 3000 μ s = 3 ms$ .
Comparison: $3000/200 = 15$ . Interrupt-driven I/O uses 15 times as much CPU time for this block, because it pays the context save and restore on every word.

Answer: (a) 200 µs. (b) 3000 µs (3 ms) of CPU time, 15 times the 200 µs that burst-mode DMA takes from the CPU.

WORKED EXAMPLE

A device raises an interrupt once every 500 µs on average. Each interrupt (save + ISR + restore) takes 4 µs of CPU time. Over one second of running, what percentage of CPU time goes to servicing this device?

Solution

$f_{CPU} = t_{int} / T_{int} = 4 μ s /500 μ s = 0.008$ .
As a percentage: $0.008 \times 100 = 0.8%$ .
Check over one second: $1 0^{6} μ s /500 μ s = 2000$ interrupts, costing $2000 \times 4 μ s = 8000 μ s = 8 ms$ , and $8/1000 = 0.8%$ . The two methods agree.

Answer: 0.8% of CPU time.

WORKED EXAMPLE

A device transfers data continuously at $4 \times 1 0^{6}$ bytes per second, using DMA in blocks of 16,000 bytes (decimal units, as given). The CPU clock is 500 MHz. For each block, the CPU spends 500 clock cycles programming the DMAC and 1500 clock cycles in the completion ISR. Ignoring the bus cycles DMA steals, what percentage of CPU time does this device use?

Solution

Time per block: $T_{block} = 16, 000/ (4 \times 1 0^{6}) = 4 \times 1 0^{- 3} s = 4 ms$ .
CPU time per block: $(500 + 1500)$ cycles $= 2000$ cycles; $2000/ (500 \times 1 0^{6}) = 4 \times 1 0^{- 6} s = 4 μ s$ .
Percentage: $4 μ s /4000 μ s \times 100 = 0.1%$ .

Answer: 0.1% of CPU time.

EXAM TIP

Before choosing a formula, identify the technique from the question's wording:

'Block/burst transfer, CPU cannot use the bus': the transfer time is $N \times t_{mem}$ .
'Cycle stealing': that same product is CPU delay, not elapsed time. The fraction of cycles stolen is $t_{c} / T_{w}$ .
'Once every $T$ , service takes $t$ ': this is an interrupt-overhead question; compute $t / T$ .
'Set-up and completion cycles per block': this is the DMA overhead formula, divided by the block time at the device's data rate.

EXAM TIP

Check what $N$ counts (words or bytes) and what $t_{mem}$ covers (one memory cycle, or a full bus cycle with wait states). Using the wrong unit gives a plausible-looking wrong answer.

For memory and block sizes, take K = $2^{10}$ unless the question says otherwise. For data rates, follow the question's own convention. State the assumption you make.

PREVIOUS-YEAR QUESTIONS

8 questions from the CS papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE CSE 2026 Set 2 · GATE CSE 2025 Set 1 · GATE CSE 2024 Set 1 · GATE CSE 2024 Set 2 · GATE CSE 2023 · GATE CSE 2022 · GATE CSE 2020 · GATE CSE 2018

GATE 2026 CS2 Q.18

GATE 2026 · CS2Q.18 · 1 mark · MCQ

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2 ?

(A)
Both S1 and S2 are true
(B)
Both S1 and S2 are false
(C)
S1 is true and S2 is false
(D)
S1 is false and S2 is true

Answer and solution

GATE 2026 CS2 Q.18: answer and solution

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GATE 2025 CS1 Q.11

GATE 2025 · CS1Q.11 · 1 mark · MCQ

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

(A)
(iii), (i), (ii)
(B)
(i), (iii), (ii)
(C)
(i), (ii), (iii)
(D)
(iii), (ii), (i)

Answer and solution

GATE 2025 CS1 Q.11: answer and solution

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GATE 2024 CS1 Q.15

GATE 2024 · CS1Q.15 · 1 mark · MCQ

Which one of the following statements is FALSE?

(A)
In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
(B)
For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
(C)
Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
(D)
The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Answer and solution

GATE 2024 CS1 Q.15: answer and solution

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GATE 2024 CS2 Q.11

GATE 2024 · CS2Q.11 · 1 mark · MCQ

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

(A)
2,56,000
(B)
3,200
(C)
25,60,000
(D)
32,000

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GATE 2024 CS2 Q.11: answer and solution

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GATE 2023 CS Q.34

GATE 2023 · CSQ.34 · 1 mark · NAT

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 μs (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 μs to process the keystroke. Let $T_{1}$ denote the fraction of a second spent in polling and processing a keystroke.

In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let $T_{2}$ denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio $\frac{T _{1}}{T _{2}}$ is ______. (Rounded off to one decimal place)

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GATE 2022 CS Q.17

GATE 2022 · CSQ.17 · 1 mark · MCQ

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

(A)
DMA based I/O transfer
(B)
Interrupt driven I/O transfer
(C)
Polling based I/O transfer
(D)
Programmed I/O transfer

Answer and solution

GATE 2022 CS Q.17: answer and solution

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GATE 2020 CS Q.3

GATE 2020 · CSQ.3 · 1 mark · MCQ

Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.

II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.

III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.

IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

(A)
I and II only
(B)
I and IV only
(C)
I and III only
(D)
III only

Answer and solution

GATE 2020 CS Q.3: answer and solution

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GATE 2018 CS Q.9

GATE 2018 · CSQ.9 · 1 mark · MCQ

The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution.

(P) The processor pushes the process status of $L$ onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of $L$ from the control stack.
(T) The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

(A)
QPTRS
(B)
PTRSQ
(C)
TRPQS
(D)
QTPRS

Answer and solution

GATE 2018 CS Q.9: answer and solution

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PRACTICE

6 questions to test yourself

PRACTICE 11 mark · MCQ

In a system using daisy-chain (serial) priority interrupts, the priority of a device is determined by:

(A)
Its physical position in the chain: devices closer to the CPU get higher priority
(B)
The numeric value of its interrupt vector
(C)
The order in which the operating system polls device status registers
(D)
A software-assigned mask that can be changed at runtime

Answer and solution

Answer: (A)

In daisy chaining, the CPU's interrupt-acknowledge (INTACK) signal is wired through the devices in series.
A device with no pending request passes INTACK on to the next device. A device with a pending request stops INTACK there and places its own vector on the bus.
INTACK reaches the devices in wiring order, starting from the CPU. So the requesting device closest to the CPU is always acknowledged first. Wiring fixes the priority, not software.
Hence (A). The vector value, a polling order and a software mask play no part in how a daisy chain fixes priority.

PRACTICE 22 marks · NAT

A DMA controller in burst (block) mode transfers a block of 4096 words from a device buffer to memory. Each memory cycle takes 40 ns, each word transfer needs exactly one memory cycle, and the CPU cannot use the bus during the burst. Ignoring bus-arbitration overhead, what is the total time (in microseconds) to complete this DMA transfer?

Answer and solution

Answer: $163.84$ (accepted range $\pm 0.01$ )

Burst mode holds the bus for the whole block, with no interleaving with the CPU.
$T = N \times t_{mem} = 4096 \times 40 ns$ .
$4096 \times 40 = 163, 840$ ns.
$163, 840 ns = 163.84 μ s$ .

PRACTICE 32 marks · MSQ

A system has a single shared system bus. Which of the following statements about cycle-stealing DMA are TRUE?

(A)
In any single bus cycle, at most one of the CPU and the DMA controller is the bus master
(B)
The CPU is interrupted once for every word the DMA controller transfers
(C)
For the same block, with every word available back to back, cycle stealing always completes the transfer sooner than burst mode
(D)
After transferring one word, the DMA controller releases the bus to the CPU and requests it again for the next word

Answer and solution

Answer: (A), (D)

(A) True. A single shared bus has one set of address, data and control lines, so only one master can drive it in a given cycle. Stealing a cycle means the DMAC is master for that cycle instead of the CPU.
(B) False. The DMAC moves each word without any CPU instruction. The CPU gets only one interrupt, when the whole block is complete.
(C) False. With words available back to back, burst mode moves them one after another with no gaps. Cycle stealing gives the bus back between words, so it finishes no sooner than burst, and generally later.
(D) True. Releasing the bus after each word and requesting it again for the next is what defines cycle stealing. In burst mode the DMAC keeps the bus for the whole block.
Correct set: A, D.

PRACTICE 41 mark · MCQ

Which statement correctly describes a VECTORED interrupt?

(A)
The CPU polls every device's status register in a fixed sequence to find which one requested service
(B)
The interrupting device supplies an address (vector) that points the CPU directly to that device's own service routine
(C)
All interrupting devices are serviced from a single, fixed service-routine address, whichever device requested
(D)
The vector address is chosen only by a software priority mask maintained by the operating system

Answer and solution

Answer: (B)

(A) describes a polled (non-vectored) scheme, not a vectored one.
(C) describes a non-vectored interrupt, where software must then find the actual source.
(D) is wrong: in a vectored interrupt the vector comes from the device or its interrupt controller, usually during an interrupt-acknowledge cycle. It does not come from a software mask.
(B) is the defining property: the hardware hands the CPU a device-specific address, so no polling is needed.

PRACTICE 52 marks · NAT

A device interrupts the CPU on average once every 250 µs. Each interrupt needs 5 µs of CPU time in total (context save + ISR execution + context restore). What percentage of CPU time is spent servicing this device?

Answer and solution

Answer: $2$ (accepted range $\pm 0.1$ )

$f_{CPU} = t_{int} / T_{int} = 5 μ s /250 μ s$ .
$5/250 = 0.02$ .
As a percentage: $0.02 \times 100 = 2%$ .

PRACTICE 62 marks · NAT

A device using cycle-stealing DMA supplies one word every 2 µs. Each word transfer steals exactly one bus cycle of 50 ns. Assume the CPU would otherwise use the bus in every cycle, and ignore bus-arbitration overhead. What percentage of the CPU's bus cycles does the DMA controller take?

Answer and solution

Answer: $2.5$ (accepted range $\pm 0.01$ )

Each word period is $T_{w} = 2 μ s = 2000$ ns, and in each one the DMAC steals one bus cycle of $t_{c} = 50$ ns.
$f_{stolen} = t_{c} / T_{w} = 50/2000 = 0.025$ .
As a percentage: $0.025 \times 100 = 2.5%$ .

OFFICIAL GATE 2027 SYLLABUS WORDING

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GATE CS

I/O interface (interrupt and DMA)

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