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GATE 2020 CS Q.3: solution and answer

GATE 2020 · CSQ.3 · 1 mark · MCQ

Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.

II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.

III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.

IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

  1. (A)

    I and II only

  2. (B)

    I and IV only

  3. (C)

    I and III only

  4. (D)

    III only

See the question in the paper
GATE 2020 CS question 3Tap to open full size

Answer and solution

ANSWER

Statements I and III are true, so the correct answer is (C) I and III only.

Official answer: CSource: Official answer key, GATE 2020 CS (IIT Delhi)

  1. Statement I: Daisy chaining connects devices along a single interrupt-acknowledge line; a device passes the acknowledge signal on only if it did not request interrupt, so the device closest to the CPU gets the highest priority. This is a standard hardware technique for assigning interrupt priority — TRUE.

  2. Statement II: A vectored interrupt means the interrupting device itself supplies a vector (an address or device identifier) to the CPU during the interrupt-acknowledge cycle, so the CPU can directly locate the correct interrupt-service routine without checking each device in turn. Polling (checking status bits one by one) is the technique used for non-vectored interrupts, not vectored ones. So statement II is FALSE.

  3. Statement III: This is the definition of polling — the CPU repeatedly reads the status/flag register of each device to see whether it needs service. This matches the statement exactly — TRUE.

  4. Statement IV: During DMA, the DMA controller must request and be granted control of the system bus from the CPU (bus request / bus grant handshake); while the DMA controller holds the bus (in cycle-stealing, burst, or block mode), the CPU relinquishes bus mastership until the transfer or burst completes. The CPU and DMA controller are never simultaneous bus masters — FALSE.

  5. True statements are I and III only, which is option (C).

KEY IDEA

Vectored interrupts let the device self-identify to the CPU (no polling needed); polling is only for non-vectored/software-poll schemes. Daisy chaining is a hardware priority-resolution mechanism. DMA requires exclusive bus mastership handed off from the CPU — never shared simultaneously.

WATCH OUT FOR

Confusing "vectored" with requiring polling (students sometimes think the CPU still must poll to confirm the vector), and assuming DMA and CPU can share the bus concurrently since both are "active" during a DMA transfer — in reality bus mastership is exclusive at any instant.

From the GATE 2020 CS paper. Every question of this paper · Download the full paper · All 8 I/O, interrupts & DMA questions, with notes

More I/O, interrupts & DMA questions