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GATE 2018 CS Q.9: solution and answer

GATE 2018 · CSQ.9 · 1 mark · MCQ

The following are some events that occur after a device controller issues an interrupt while process is under execution.

(P) The processor pushes the process status of onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of from the control stack.
(T) The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

  1. (A)

    QPTRS

  2. (B)

    PTRSQ

  3. (C)

    TRPQS

  4. (D)

    QTPRS

See the question in the paper
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Answer and solution

ANSWER

The correct order of events is Q, P, T, R, S — the processor finishes the current instruction (Q), pushes L's process status onto the control stack (P), loads the new PC value for the ISR (T), executes the interrupt service routine (R), and finally pops L's status to resume (S). This matches option (A) QPTRS.

Official answer: ASource: Official answer key, GATE 2018 CS (IIT Guwahati)

  1. An interrupt is checked for and honored only at instruction boundaries, so the processor first finishes executing the current instruction: Q.

  2. Before the processor can safely transfer control elsewhere, it must preserve process L's context so execution can later resume — it pushes L's process status onto the control stack: P.

  3. With L's state safely saved, the processor loads the new PC value corresponding to the interrupt service routine's entry point (vectors to the ISR): T.

  4. With PC now pointing to the ISR, the processor executes the interrupt service routine: R.

  5. After the ISR completes, the processor restores the interrupted process's context by popping L's saved status from the control stack, allowing L to resume: S.

  6. The physical order is therefore Q, P, T, R, S, which matches option (A) QPTRS.

KEY IDEA

Interrupt handling sequence: an interrupt is only recognized at an instruction boundary, so the processor completes the current instruction (Q) first; it then saves the interrupted process's context (P) before it can safely redirect control, loads the ISR's start address into the PC (T), runs the ISR (R), and finally restores the saved context (S) to resume the interrupted process. Save-before-jump is the essential ordering constraint.

WATCH OUT FOR

Placing "loads new PC" (T) before "pushes process status" (P), reasoning that the jump happens first — but the processor must save the interrupted context onto the stack before it can safely redirect the PC to the ISR, otherwise the return address/status would be lost.

From the GATE 2018 CS paper. Every question of this paper · Download the full paper · All 8 I/O, interrupts & DMA questions, with notes

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