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GATE 2026 CS2 Q.18: solution and answer

GATE 2026 · CS2Q.18 · 1 mark · MCQ

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2 ?

  1. (A)

    Both S1 and S2 are true

  2. (B)

    Both S1 and S2 are false

  3. (C)

    S1 is true and S2 is false

  4. (D)

    S1 is false and S2 is true

See the question in the paper
GATE 2026 CS2 question 18Tap to open full size

Answer and solution

ANSWER

S1 is true and S2 is false → Option (C)

Official answer: CSource: Official answer key, GATE 2026 CS2 (IIT Guwahati)

  1. S1: A vectored interrupt mechanism has the interrupting device supply the address (vector) of its own ISR directly to the CPU during the interrupt-acknowledge cycle, so the CPU can jump almost immediately to the correct ISR.

  2. In a non-vectored interrupt mechanism, the CPU always transfers control to one fixed/predetermined address first, and additional steps (software polling of device status registers, or a priority-encoding step) are needed to identify which device caused the interrupt before the correct ISR can begin.

  3. These extra identification steps mean starting the ISR usually takes more time in the non-vectored scheme than in the vectored scheme — so S1 is TRUE.

  4. S2: Daisy-chaining is a hardware-based interrupt-priority and identification scheme: devices are connected in series, and a single interrupt-acknowledge signal from the CPU propagates serially through the chain.

  5. The first device in the chain that is requesting service intercepts (blocks) the propagating signal and identifies itself (e.g., by gating its vector onto the bus); devices further down the chain never see the signal that cycle.

  6. This hardware propagation is fundamentally different from software polling, where the CPU itself sequentially queries each device's status register to find the interrupting source — daisy-chaining exists specifically to avoid that CPU overhead.

  7. Since the CPU does not poll all devices individually in a daisy-chain scheme, S2's claim is FALSE.

  8. Combining the two results: S1 is true and S2 is false, which is option (C).

KEY IDEA

Vectored interrupts let the interrupting device supply its ISR address/vector directly, so dispatch is fast; non-vectored interrupts force the CPU into extra identification steps before it can jump to the right ISR. Daisy-chaining resolves priority and identifies the interrupting device entirely in hardware (the acknowledge signal is passed serially and intercepted by the requesting device) — it is the alternative to CPU software polling, not an instance of it.

WATCH OUT FOR

Confusing daisy-chaining (a hardware priority/identification scheme) with software polling (where the CPU itself queries each device in sequence); the two are often taught back to back and are easy to conflate because both eventually "check devices one by one" — but in daisy-chaining that checking is done by hardware propagation of a signal, not by the CPU executing a polling loop.

From the GATE 2026 CS2 paper. Every question of this paper · Download the full paper · All 8 I/O, interrupts & DMA questions, with notes

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