Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
2,56,000
3,200
25,60,000
32,000
ANSWER
The DMA controller transfers bits per second, written 25,60,000 in Indian grouping, so the answer is option (C).
Official answer: CSource: Official answer key, GATE 2024 CS2 (IISc Bengaluru)
A 4 MHz processor completes clock cycles every second.
In cycle stealing, the DMA controller takes some of these cycles to use the bus. Here it takes 1% of them: cycles per second.
In each stolen cycle it transfers 8 bytes, which is bits.
Data transfer rate .
The options use Indian digit grouping, where is written 25,60,000. That is option (C). Option (A), 2,56,000, is ten times smaller and would need only 4,000 stolen cycles per second (0.1%).
KEY IDEA
With cycle stealing, DMA throughput is (cycles stolen per second) × (data moved per cycle). Cycles stolen per second = clock rate × the fraction of cycles given to DMA.
WATCH OUT FOR
The usual mistakes are misreading the Indian digit grouping (25,60,000 is 2.56 million and 2,56,000 is 256 thousand) and forgetting to turn bytes into bits. Leaving the answer in bytes gives 3,20,000 bytes/s, which is not an option. Taking 0.1% instead of 1% leads to option (A).
From the GATE 2024 CS2 paper. Every question of this paper · Download the full paper · All 8 I/O, interrupts & DMA questions, with notes
