GATE CS

ALU design and the control unit

Hardwired and microprogrammed

A CPU executes an instruction as a sequence of register transfers. The ALU does the arithmetic and logic. Its adder is either ripple-carry (little hardware, delay grows as n) or carry look-ahead (more hardware; delay is constant for a single level with unlimited fan-in, and O(log n) when built in levels). The control unit produces the control signals for each step, either from logic wired around a state counter (hardwired: fast but rigid) or by reading microinstructions from a control memory (microprogrammed: flexible, slower). Microinstructions can be horizontal (one bit per signal) or encoded (vertical), and control-memory size = number of words × word width.

5 previous-year questions · 5 solved · 5 practice questions

ALU Design: Adders, Subtraction and Carry Look-Ahead

The Arithmetic and Logic Unit (ALU) performs arithmetic operations (add, subtract, increment, decrement) and logic operations (AND, OR, XOR, NOT, shifts). An $n$ -bit ALU is commonly built from $n$ identical bit-slices. In each slice, a multiplexer driven by function-select lines chooses which operation's result reaches the output, so $k$ select lines can choose among at most $2^{k}$ operations. Subtraction is done by adding the 2's complement, so the adder is the core of the arithmetic side and its carry chain sets the ALU's speed. The two adder designs to know are the ripple-carry adder (little hardware, slow) and the carry look-ahead adder (more hardware, fast).

Convention used throughout (unless a question says otherwise): numbers are in 2's complement. Bits are numbered $0$ (LSB) to $n - 1$ (MSB), $C_{0}$ is the carry into bit 0 and $C_{n}$ is the final carry-out. A full adder (FA) takes $A_{i}, B_{i}, C_{i}$ and produces $S_{i}$ and $C_{i + 1}$ a fixed delay after its inputs are stable. All delays are worst case. When delays are counted in gates, each gate (including XOR) counts as 1 gate delay and fan-in is unlimited. If a question gives its own figures, use those.

FULL ADDER EQUATIONS

S_{i} = A_{i} \oplus B_{i} \oplus C_{i}, C_{i + 1} = A_{i} B_{i} + B_{i} C_{i} + A_{i} C_{i}

One bit-slice of any adder. Both outputs need all three inputs to be stable.

SUBTRACTION AND OVERFLOW (2'S COMPLEMENT)

A - B = A + \overline{B} + 1 (use C_{0} = 1), V = C_{n} \oplus C_{n - 1}

An adder/subtractor passes each $B_{i}$ through an XOR gate with a mode line $M$ and sets $C_{0} = M$ : $M = 0$ adds and $M = 1$ subtracts. $V = 1$ signals signed (2's complement) overflow. For unsigned numbers, $C_{n} = 1$ after an addition means the result does not fit in $n$ bits. After a subtraction done as $A + \overline{B} + 1$ , $C_{n} = 1$ means $A \geq B$ (no borrow).

Ripple-carry adder (RCA): $n$ full adders are cascaded, with the carry-out of bit $i$ feeding the carry-in of bit $i + 1$ . In the worst case (for example $A = 11 \dots 1$ , $B = 00 \dots 01$ ), a carry generated at bit 0 must ripple through every stage, so the carry chain is the critical path.

RIPPLE-CARRY ADDER WORST-CASE DELAY

T_{C_{n}} = n t_{c}, T_{S_{n - 1}} = (n - 1) t_{c} + t_{s}

$t_{c}$ is one FA's carry delay and $t_{s}$ is its sum delay, measured from when its carry-in is stable (its $A_{i}$ , $B_{i}$ are already stable). If one figure $t_{F A}$ is given for both outputs, both times equal $n t_{F A}$ . The delay grows linearly with $n$ .

Carry look-ahead adder (CLA): instead of waiting for the carry to ripple, every carry is written directly in terms of $C_{0}$ and per-bit generate and propagate signals, so all carries can be formed at once.

GENERATE, PROPAGATE AND SUM

G_{i} = A_{i} B_{i}, P_{i} = A_{i} \oplus B_{i}, S_{i} = P_{i} \oplus C_{i}

$G_{i} = 1$ : bit $i$ produces a carry whatever $C_{i}$ is. $P_{i} = 1$ : bit $i$ passes an incoming carry on to $C_{i + 1}$ . Some texts use $P_{i} = A_{i} + B_{i}$ . The carry equations below still hold with that choice, but the sum can then no longer be formed as $P_{i} \oplus C_{i}$ .

CARRY RECURRENCE AND ITS LOOK-AHEAD EXPANSION

C_{i + 1} C_{1} C_{2} C_{3} C_{4} = G_{i} + P_{i} C_{i} = G_{0} + P_{0} C_{0} = G_{1} + P_{1} G_{0} + P_{1} P_{0} C_{0} = G_{2} + P_{2} G_{1} + P_{2} P_{1} G_{0} + P_{2} P_{1} P_{0} C_{0} = G_{3} + P_{3} G_{2} + P_{3} P_{2} G_{1} + P_{3} P_{2} P_{1} G_{0} + P_{3} P_{2} P_{1} P_{0} C_{0}

Each expanded carry is a two-level AND-OR expression in the $G$ 's, $P$ 's and $C_{0}$ , so every carry is ready 2 gate delays after the $P$ , $G$ signals, whatever its position. The cost is fan-in: $C_{i}$ has $i + 1$ product terms and its largest AND gate has $i + 1$ inputs.

SINGLE-LEVEL CLA DELAY (CONVENTION ABOVE)

T_{CLA} = P_{i}, G_{i} 1 + all carries 2 + S_{i} = P_{i} \oplus C_{i} 1 = 4 gate delays

This is independent of $n$ only because fan-in is assumed unlimited. If a question counts an XOR as more than one gate delay, substitute its figure in the first and last terms.

BLOCK (GROUP) GENERATE AND PROPAGATE FOR A 4-BIT BLOCK

G^{*} = G_{3} + P_{3} G_{2} + P_{3} P_{2} G_{1} + P_{3} P_{2} P_{1} G_{0}, P^{*} = P_{3} P_{2} P_{1} P_{0}, C_{4} = G^{*} + P^{*} C_{0}

Fan-in limits force wide adders to be built from $k$ -bit CLA blocks. Each block's $G^{*}$ , $P^{*}$ take 2 gate delays after the bit-level $P_{i}$ , $G_{i}$ . A second-level look-ahead unit applies the same carry equations to the block signals, giving the carry into every block at once instead of rippling between blocks. With a fixed block size $k$ , the number of look-ahead levels grows as $lo g_{k} n$ , so the delay grows as $O (lo g n)$ .

How to solve a CLA timing question

Draw the chain of stages: bit-level $P_{i}$ , $G_{i}$ → block $P^{*}$ , $G^{*}$ (if there is a second level) → look-ahead unit giving the carry into each block → carries inside the block → sum bits.
Take each stage's delay from the question. If none is given, use the convention above: 1 gate delay for $P_{i}$ and $G_{i}$ , 2 for any AND-OR carry or group level, 1 for the final XOR.
A stage can start only when its latest input is stable. For example, a block's internal carries need both its own $P_{i}$ , $G_{i}$ and its carry-in, and the carry-in is usually the later one.
The worst case is the path to the sum bits of the block whose carry-in arrives last. Stages that run in parallel in different blocks are never added together.

EXAM TIP

Some questions combine ripple-carry blocks with a look-ahead unit between blocks, and give one delay per full adder and a different delay per look-ahead level. Check which figure applies to which stage before adding anything.

Datapath and Register Transfers

The datapath is the set of registers, buses, ALU and multiplexers that move and transform data. The control unit decides, cycle by cycle, which register loads, which register drives a bus and which ALU operation is performed. A typical datapath has general-purpose registers, a Memory Address Register (MAR), a Memory Data (Buffer) Register (MDR/MBR), the Program Counter (PC), the Instruction Register (IR), and one or more internal buses that connect them through the ALU.

A register transfer is written in micro-operation notation, for example MAR ← PC (copy PC into MAR) or AC ← AC + DR (add DR into the accumulator). A transfer that completes in one clock cycle is a micro-operation. Every machine instruction runs as a sequence of micro-operations, and producing that sequence is the control unit's job, whether it is hardwired or microprogrammed.

R2 ← R1: the content of R1 is copied into R2 and R1 is unchanged.
A comma joins micro-operations done in the SAME clock cycle, for example MAR ← PC, PC ← PC + 1. This is possible only if the hardware has separate paths for them (here, a PC incrementer that does not use the shared bus).
P: R2 ← R1 means the transfer happens only when the control condition P is 1, for example T5 · D_ADD: AC ← AC + MDR (at timing step T5, and only for an ADD instruction).
On a single shared bus, only ONE register can drive the bus in a cycle, but any number of registers can load from it in that cycle. So R2 ← R1 over the bus takes one cycle, and two transfers from different sources need two cycles.

EXAM TIP

To count cycles on a single-bus datapath, count how many different sources must drive the bus, one per cycle. One value on the bus can load several destinations in the same cycle.

The Instruction Cycle

Every instruction runs through the same phases: Fetch → Decode → (Operand fetch, if needed) → Execute → (Interrupt check). The control unit steps through these phases, issuing the correct control signals in each cycle, and then returns to Fetch.

Typical micro-operations (single-bus, accumulator machine)

Fetch: MAR ← PC; then MDR ← M[MAR], PC ← PC + 1 (the increment uses a separate incrementer); then IR ← MDR.
Decode: the opcode bits of IR are decoded to select the execute sequence. This is combinational and needs no register transfer of its own.
Operand fetch with indirect addressing: MAR ← IR(address); then MDR ← M[MAR]; then MAR ← MDR (MAR now holds the effective address).
Execute, for example ADD: MDR ← M[MAR]; then AC ← AC + MDR.
Interrupt check: at the end of the instruction, if an interrupt is pending and enabled, the control unit saves the PC and transfers control to the interrupt handler instead of fetching the next instruction.

A hardwired and a microprogrammed control unit can implement exactly the same micro-operation sequence for an instruction set. They differ only in how the control signals for each step are produced.

Hardwired Control Unit

A hardwired control unit produces control signals directly from combinational logic whose inputs are the decoded opcode (from IR), the current timing state ( $T_{0}, T_{1}, T_{2}, \dots$ ) and the condition flags. It is a finite state machine (Moore or Mealy): a state register or sequence counter records the current step of the instruction cycle, and logic computes the next state and the control outputs.

Structure of a hardwired control unit

A sequence counter (or state register) steps through $T_{0}, T_{1}, T_{2}, \dots$ and is cleared to $T_{0}$ after an instruction's last step (or on an interrupt).
An opcode decoder turns the IR opcode into one-hot lines such as D_ADD or D_STORE.
Each control signal is an OR of AND terms of {timing state} · {decoded opcode} · {flags}. For example, in the ADD sequence of the worked example below, MAR is loaded at T0 for every instruction and at T3 for ADD, so MAR_load = T0 + T3 · D_ADD + … (one term for each place it is used).
The counter is cleared at the end of each instruction's sequence, so instructions of different lengths simply use different numbers of timing states.

Hardwired vs microprogrammed control

Aspect	Hardwired control	Microprogrammed control
Implementation	Logic and a state counter wired to the control lines	Control words (microinstructions) stored in a control memory, read out and applied each step
Speed	Faster: no control-memory read in each step	Slower: each step includes a control-memory access
Modifying the instruction set	Hard: the logic must be redesigned	Easy: rewrite the microprogram
Design regularity	Irregular logic; harder to design and debug for large instruction sets	Regular and systematic; suits large, complex instruction sets
Extra hardware	No control memory	Control memory plus a control address register and sequencing logic
Typical use	RISC and speed-critical designs	CISC designs with large instruction sets

EXAM TIP

Timing signals $T_{0}, T_{1}, \dots$ may be produced by a ring counter (one flip-flop per state, one-hot) instead of a binary counter and decoder. It is the same hardwired model with a different state encoding.

Microprogrammed Control Unit

A microprogrammed control unit stores the control signals for each step as a bit pattern called a microinstruction, held in a control memory (control store), usually a ROM. The sequence of microinstructions that implements one machine instruction is its microprogram. A control address register (CAR, also called the micro-program counter, μPC) holds the address of the current microinstruction.

Structure

Control Address Register (CAR / μPC): the address of the current microinstruction.
Control memory: one word per microinstruction.
Control buffer/data register: holds the microinstruction just read. Its fields drive the control lines and the next-address logic.
Sequencing logic: chooses the next CAR value. The choices are CAR + 1 (the next step of the same microprogram); a branch to the first microinstruction of a new machine instruction, found by mapping the opcode; or a conditional branch on a status flag, using a condition-select field and a next-address field.

Mapping: after a fetch, the opcode must be converted into the control-memory address of the first microinstruction of that instruction's microprogram. This is done by a mapping function, for example the opcode bits placed in fixed positions of the address, or a lookup ROM. It plays the role that the opcode decoder plays in hardwired control.

CONTROL MEMORY SIZE

Size (bits) = W \times w, w = (control field bits) + (condition-select bits) + (next-address bits)

$W$ is the number of words (microinstructions) and $w$ is the width of one microinstruction. When a question gives the number of address bits $a$ of the CAR instead, $W = 2^{a}$ . Convert to bytes by dividing by 8, and to KB with K = $2^{10}$ .

NEXT-ADDRESS AND CONDITION-SELECT FIELD WIDTHS

next-address bits = ⌈ lo g_{2} W ⌉, condition-select bits = ⌈ lo g_{2} c ⌉

$W$ is the number of control-memory words that must be addressable. $c$ is the number of branch choices the field must select among, counting 'unconditional' (or 'no branch') as a choice when the question includes it.

Horizontal and Vertical Microinstructions

The control field of a microinstruction can be encoded in different ways. Encoding trades control-memory width against decoding hardware and parallelism.

Horizontal vs vertical microinstruction format

Aspect	Horizontal	Vertical (encoded)
Encoding	One bit per control signal; any combination can be active together	Signals are encoded into fields; a decoder produces the actual control lines
Control-field width	One bit per signal (wide)	A field that selects one of $k$ choices needs $⌈ lo g_{2} k ⌉$ bits (narrow)
Parallelism	High: many micro-operations in one microinstruction	Low: only one signal per encoded field can be active
Decoding	None needed	A decoder per field, adding a small delay
Microinstructions per machine instruction	Fewer	Often more
Control memory	Wider words	Narrower words, though often more of them

Most practical designs are partially encoded. Signals that can never be active together are grouped into fields, each field is decoded separately, and signals that must be able to act together are placed in different fields. This lies between fully horizontal and fully vertical formats.

CONTROL-FIELD WIDTH: HORIZONTAL VS ENCODED

w_{horizontal} = j \sum k_{j}, w_{encoded} = j \sum ⌈ lo g_{2} (k_{j} + 1)⌉

Group $j$ holds $k_{j}$ mutually exclusive signals. The $+ 1$ is the code for 'none of this group active'. Drop it (use $⌈ lo g_{2} k_{j} ⌉$ ) only if the question says exactly one signal of the group is always active, or says no-operation need not be encoded.

Computing a microinstruction's width

For each encoded field, count the choices it must represent (its signals, plus 'none' if needed) and take $⌈ lo g_{2} (choices)⌉$ bits.
Add one bit for each signal kept unencoded (horizontal).
Add the condition-select bits and the next-address bits ( $⌈ lo g_{2} W ⌉$ ).
Multiply the total width by the number of words for the control-memory size, then convert to bytes or KB as asked (K = $2^{10}$ ).

EXAM TIP

$k$ independent signals that may be active together need $k$ bits. If at most one of them can be active at a time, an encoded field needs only $⌈ lo g_{2} (k + 1)⌉$ bits, or $⌈ lo g_{2} k ⌉$ if 'none' is never required.

Worked Examples

WORKED EXAMPLE

A CPU has one internal bus that connects all registers and the ALU. Only one register can drive the bus in a clock cycle, and loads happen at the end of the cycle from the value on the bus. The ALU takes its operands from two input latches X and Y, and its output can drive the bus directly. How many clock cycles does R3 ← R1 + R2 take, and what happens in each?

Solution

Both operands must be in the ALU's input latches before it can add. Only one register can drive the bus per cycle, so R1 and R2 need separate cycles.
Cycle 1: R1 drives the bus and X loads it (X ← R1).
Cycle 2: R2 drives the bus and Y loads it (Y ← R2).
Cycle 3: the ALU drives the bus with X + Y and R3 loads it (R3 ← X + Y). Only one source (the ALU) uses the bus in this cycle.
Variant: in the common design where one ALU input comes straight from the bus and the result goes into an output register Z, the steps are Y ← R1, then Z ← Y + R2, then R3 ← Z. That is also 3 cycles.

Answer: 3 clock cycles: X ← R1; Y ← R2; R3 ← X + Y.

WORKED EXAMPLE

A hardwired control unit runs a direct-addressing ADD as follows. T0: MAR ← PC. T1: MDR ← M[MAR], PC ← PC + 1. T2: IR ← MDR (decoding is combinational and takes no extra cycle). T3: MAR ← IR(address). T4: MDR ← M[MAR]. T5: AC ← AC + MDR, after which the counter clears to T0. AC is loaded only by ADD, and D_ADD is the decoded ADD line. Write the expression for AC_load.

Solution

AC must load exactly at the step where AC ← AC + MDR happens, and only for ADD.
In the given sequence that step is T5.
So AC_load must be 1 when the state is T5 AND the instruction is ADD.
D_ADD is valid from T2 onward, once IR has been loaded, so it is valid at T5.

Answer: AC_load = T5 · D_ADD

WORKED EXAMPLE

A microprogrammed control unit has 256 words of control memory. Its control signals fall into three groups of mutually exclusive signals: 7, 12 and 3 signals. In each group, 'none active' must also be possible. A branch field selects among 4 status conditions or 'unconditional'. Find the microinstruction width (a) with the groups encoded and (b) fully horizontal.

Solution

Encoded groups: $⌈ lo g_{2} 8 ⌉ = 3$ , $⌈ lo g_{2} 13 ⌉ = 4$ , $⌈ lo g_{2} 4 ⌉ = 2$ , so the control field is 9 bits.
Condition select: 5 choices, so $⌈ lo g_{2} 5 ⌉ = 3$ bits.
Next address: $⌈ lo g_{2} 256 ⌉ = 8$ bits.
(a) Encoded width = 9 + 3 + 8 = 20 bits.
(b) Horizontal control field = 7 + 12 + 3 = 22 bits, so the width = 22 + 3 + 8 = 33 bits.

Answer: (a) 20 bits, (b) 33 bits

PREVIOUS-YEAR QUESTIONS

5 questions from the CS papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE CSE 2025 Set 1 · GATE CSE 2025 Set 2 · GATE CSE 2022 · GATE CSE 2020

GATE 2025 CS1 Q.27

GATE 2025 · CS1Q.27 · 1 mark · MSQ

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

GATE 2025 CS1 question 27: A data path diagram. — Figure from the GATE 2025 CS1 paper. It is part of the question.

(A)
The data path can implement arithmetic operations involving two registers.
(B)
The data path can implement arithmetic operations involving one register and one immediate value.
(C)
The data path can implement arithmetic operations involving two immediate values.
(D)
The data path can only implement arithmetic operations involving one register and one immediate value.

Answer and solution

GATE 2025 CS1 Q.27: answer and solution

GATE 2025 CS2 Q.32

GATE 2025 · CS2Q.32 · 1 mark · NAT

The following two signed 2's complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth's algorithm:

M: 1100 1101 1110 1101 and Q: 1010 0100 1010 1010

The total number of addition and subtraction operations to be performed is ___________. (Answer in integer)

Answer and solution

GATE 2025 CS2 Q.32: answer and solution

See the question in the paper

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GATE 2025 CS2 Q.32: answer and solution

GATE 2022 CS Q.18

GATE 2022 · CSQ.18 · 1 mark · MCQ

Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow?

(A)
R1 = 1011 and R2 = 1110
(B)
R1 = 1100 and R2 = 1010
(C)
R1 = 0011 and R2 = 0100
(D)
R1 = 1001 and R2 = 1111

Answer and solution

GATE 2022 CS Q.18: answer and solution

See the question in the paper

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GATE 2020 CS Q.4

GATE 2020 · CSQ.4 · 1 mark · MCQ

Consider the following data path diagram.

Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. R2r, TEMP1r, ALUadd, TEMP2w
2. R1r, TEMP1w
3. PCr, MARw, MEMr
4. TEMP2r, R0w
5. MDRr, IRw

Which one of the following is the correct order of execution of the above steps?

GATE 2020 CS question 4: A single-bus datapath diagram. — Figure from the GATE 2020 CS paper. It is part of the question.

(A)
2, 1, 4, 5, 3
(B)
1, 2, 4, 3, 5
(C)
3, 5, 2, 1, 4
(D)
3, 5, 1, 2, 4

Answer and solution

GATE 2020 CS Q.4: answer and solution

GATE 2020 CS Q.29

GATE 2020 · CSQ.29 · 2 marks · MCQ

Consider three registers R1, R2, and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.

If $R 3 = \frac{R 1}{R 2}$ , what is the value stored in R3?

(A)
0x40800000
(B)
0xC0800000
(C)
0x83400000
(D)
0xC8500000

Answer and solution

GATE 2020 CS Q.29: answer and solution

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GATE 2020 CS Q.29: answer and solution

PRACTICE

5 questions to test yourself

PRACTICE 11 mark · MCQ

A 32-bit ripple-carry adder is built from 32 full adders. Each full adder produces both its sum and its carry-out 2 ns after its own inputs (including its carry-in) are stable. What is the worst-case time after the inputs are applied until both the final carry-out $C_{32}$ and the most significant sum bit $S_{31}$ are stable?

(A)
32 ns
(B)
64 ns
(C)
16 ns
(D)
2 ns

Answer and solution

Answer: (B)

Number the bits 0 to 31. In the worst case a carry generated at bit 0 ripples through every stage.
$C_{i + 1}$ is stable 2 ns after $C_{i}$ , so $C_{32}$ is stable at $32 \times 2 = 64$ ns.
$S_{31}$ needs $C_{31}$ , which is stable at $31 \times 2 = 62$ ns, so $S_{31}$ is stable at $62 + 2 = 64$ ns.
Both are stable at 64 ns.

PRACTICE 22 marks · NAT

A 16-bit adder is built from four 4-bit carry look-ahead blocks joined by a second-level carry look-ahead unit. Count every gate (including XOR) as 1 gate delay. The bit-level $p_{i}$ , $g_{i}$ are ready 1 gate delay after the operands are applied. Each block's group signals $P^{*}$ , $G^{*}$ are ready 2 gate delays after its $p_{i}$ , $g_{i}$ . The second-level unit produces the carry into every block 2 gate delays after its inputs ( $C_{0}$ and all $P^{*}$ , $G^{*}$ ) are stable. Inside a block, the internal carries are ready 2 gate delays after both the block's $p_{i}$ , $g_{i}$ and its carry-in are stable, and the sum bits 1 gate delay after that. $C_{0}$ is available together with the operands. What is the worst-case delay, in gate delays, until all 16 sum bits are stable?

Answer and solution

Answer: $8$

$p_{i}$ , $g_{i}$ ready at 1.
Block $P^{*}$ , $G^{*}$ ready at 1 + 2 = 3.
The second-level unit gives the carry into blocks 1, 2 and 3 at 3 + 2 = 5. Block 0's carry-in is $C_{0}$ , available at 0.
Blocks 1 to 3: their internal carries wait for the later of $p_{i}$ , $g_{i}$ (1) and the carry-in (5), so they are ready at 5 + 2 = 7, and the sums at 7 + 1 = 8.
Block 0 finishes earlier: carries at 1 + 2 = 3, sums at 4.
Worst case = 8 gate delays.

PRACTICE 32 marks · MSQ

Which of the following statements about a hardwired control unit are true?

(A)
Adding a new instruction generally requires redesigning the control logic or state diagram
(B)
For comparable technology, hardwired control is typically faster than microprogrammed control
(C)
The control signals are produced by reading a control memory addressed by a micro-program counter
(D)
Hardwired control is easier to modify for a new instruction than microprogrammed control

Answer and solution

Answer: (A), (B)

A: In a hardwired unit, the control signals come from logic built around the opcode, the timing state and the flags. A new instruction means redesigning that logic. True.
B: There is no control-memory read in each step, so for the same technology hardwired control is generally faster. True.
C: Reading control words from a control memory addressed by a micro-program counter describes MICROPROGRAMMED control, not hardwired. False.
D: Changing a hardwired unit means redesigning logic, whereas a microprogrammed unit only needs its microprogram rewritten. Hardwired control is therefore harder to modify, not easier. False.

PRACTICE 42 marks · NAT

A microprogrammed control unit holds 300 microinstructions. Each microinstruction specifies 40 independent control signals and has a next-address field that can point to any of the 300 microinstructions, and it has no other fields. With a fully HORIZONTAL format (one bit per control signal) and the minimum number of next-address bits, what is the width of one microinstruction in bits?

Answer and solution

Answer: $49$

Horizontal control field: 40 bits.
Next address: $⌈ lo g_{2} 300 ⌉ = 9$ bits, since $2^{8} = 256 < 300 \leq 512 = 2^{9}$ .
Width = 40 + 9 = 49 bits.

PRACTICE 51 mark · MCQ

A control memory holds 512 microinstructions, each 60 bits wide, with no padding. What is its size in bytes (1 byte = 8 bits)?

(A)
3840 bytes
(B)
3072 bytes
(C)
4096 bytes
(D)
30720 bytes

Answer and solution

Answer: (A)

Total bits = 512 × 60 = 30720.
Bytes = 30720 / 8 = 3840.
Equivalently, 3840 / 1024 = 3.75 KB with K = $2^{10}$ .

OFFICIAL GATE 2027 SYLLABUS WORDING

Copied from the GATE 2027 syllabus; see all 2027 syllabi.

GATE CS

Design of arithmetic and logic unit (ALU). Design of control unit – hardwired and microprogrammed

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