GATE 2024 CS1 Q.56: solution and answer

Official answer: 3.00Source: Official answer key, GATE 2024 CS1 (IISc Bengaluru)

1. CPI_ideal (with a perfect cache, i.e. no memory stalls at all) is given directly in the stem: ${\text{CPI}}_{ideal}=2$.

2. Instruction-cache stall cycles per instruction: every instruction must be fetched, so the instruction-cache miss rate applies to all instructions. ${\text{Stalls}}_{instr}=0.02\times 100=2$ cycles per instruction.

3. Data-cache stall cycles per instruction: only load/store instructions access the data cache, so the data-cache miss rate is scaled by the load/store fraction. ${\text{Stalls}}_{data}=0.25\times 0.08\times 100=2$ cycles per instruction.

4. Real CPI (with the actual instruction and data caches, misses included) is the ideal CPI plus both stall contributions: $${\text{CPI}}_{real}={\text{CPI}}_{ideal}+{\text{Stalls}}_{instr}+{\text{Stalls}}_{data}=2+2+2=6$$

5. Since the clock cycle time and the instruction count are unchanged between the real machine and the perfect-cache machine, execution time is proportional to CPI. So the speedup from a perfect cache is $$\text{Speedup}=\frac{{\text{CPI}}_{real}}{{\text{CPI}}_{ideal}}=\frac{6}{2}=3.00$$