A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is ____.
GATE 2022 CS Q.61: solution and answer
Answer and solution
ANSWER
Speedup = CPI(X₁)/CPI(X₂) = 1.6/1.12 ≈ 1.43.
Official answer: 1.42 to 1.45Source: Official answer key, GATE 2022 CS (IIT Kharagpur)
Compute the CPI of . Without a BPU, every branch (30% of instructions) stalls for 2 cycles, so:
Model the branch outcomes on . The BPU gives 0 stall cycles for a correctly predicted branch, and the problem states there is "neither any savings nor any additional stalls for wrong predictions" — i.e. a mispredicted branch stalls exactly as it did on , for 2 cycles. With 80% prediction accuracy, the expected stall per branch is:
Compute the CPI of , applying that expected stall only to the 30% branch fraction:
Both processors run at the same clock frequency and execute the same program (same instruction count ), so execution time is proportional to CPI alone:
Hence:Evaluate and round to two decimal places:
KEY IDEA
Speedup with the same clock frequency and same program reduces to a ratio of CPIs; build each CPI as (base CPI) + (branch fraction) × (expected stall cycles per branch), where the expected stall on the predictor-equipped processor is a probability-weighted average over the correct/incorrect prediction outcomes.
WATCH OUT FOR
Assuming the BPU also improves the misprediction penalty (e.g. treating it as 0 or as some reduced value), when the problem explicitly says a wrong prediction gets neither savings nor extra stall — i.e. it costs the same 2 cycles it always did. Another common slip is applying the 2-cycle/0.4-cycle stall to 100% of instructions instead of scaling by the 30% branch fraction, or forgetting that clock frequency being equal lets CPI ratios stand in directly for the speedup.
From the GATE 2022 CS paper. Every question of this paper · Download the full paper · All 12 Pipelining questions, with notes
More Pipelining questions
- GATE 2018 CS Q.50 · NAT · 2 marksThe instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction…
- GATE 2026 CS1 Q.16 · MCQ · 1 markWhich one of the following dependencies among the register operands of different instructions can cause a…
- GATE 2026 CS1 Q.60 · NAT · 2 marksThe EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the…
- GATE 2026 CS2 Q.57 · NAT · 2 marksA non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles…
