GATE 2026 CS2 Q.57: solution and answer

GATE 2026 · CS2Q.57 · 2 marks · NAT

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ____________. (rounded off to two decimal places)

Note: 1G= $1 0^{9}$

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Answer and solution

ANSWER

The speed-up obtained by the pipelined design over the non-pipelined design is 2.34.

Official answer: 2.30 to 2.40Source: Official answer key, GATE 2026 CS2 (IIT Guwahati)

Non-pipelined execution time per instruction: with CPI = 5 and clock frequency f = 1.6 GHz, $T_{n p} = \frac{C P I}{f} = \frac{5}{1.6 GHz} = 3.125 ns$
Pipelined design's ideal CPI is 1 (target of one instruction per clock cycle). However, 30% of instructions each incur an extra stall of 2 cycles, adding an average of $0.30 \times 2 = 0.6$ cycles per instruction to the CPI.
Average CPI for the pipelined design: $C P I_{p} = 1 + 0.6 = 1.6$ (equivalently, $0.7 \times 1 + 0.3 \times 3 = 1.6$ , since 70% of instructions take 1 cycle and 30% take $1 + 2 = 3$ cycles).
Pipelined execution time per instruction, with clock frequency $f_{p} = 1.2 GHz$ : $T_{p} = \frac{C P I _{p}}{f _{p}} = \frac{1.6}{1.2 GHz} = 1.3333 ns$
Speed-up is the ratio of execution times: $Speed-up = \frac{T _{n p}}{T _{p}} = \frac{3.125}{1.3333} = 2.34375$
Rounded to two decimal places, the speed-up is $2.34$ .

KEY IDEA

Speed-up from pipelining = (execution time per instruction, non-pipelined) / (execution time per instruction, pipelined), where execution time per instruction = CPI / clock frequency. The pipelined design's effective CPI must include the extra stall cycles caused by hazards, not just the ideal CPI = 1.

WATCH OUT FOR

Forgetting to add the hazard-stall penalty to the pipelined CPI (using CPI = 1 for the pipelined design instead of 1 + 0.3×2 = 1.6), which gives a wrong speed-up of 3.125/(1/1.2) = 2.4 instead of the correct 2.34; or comparing raw clock frequencies (1.6/1.2) instead of execution times per instruction.

From the GATE 2026 CS2 paper. Every question of this paper · Download the full paper · All 12 Pipelining questions, with notes

GATE 2026 CS2 Q.57: solution and answer

Answer and solution

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