GATE 2025 CS2 Q.56: solution and answer

GATE 2025 · CS2Q.56 · 2 marks · NAT

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)

See the question in the paper

Tap to open full size

Answer and solution

ANSWER

The time taken to process 1000 instructions is 261.04 microseconds.

Official answer: 260.20 to 261.20Source: Official answer key, GATE 2025 CS2 (IIT Roorkee)

Clock period must accommodate the slowest stage plus the inter-stage latch delay: $T_{c l k} = max (180, 250, 150, 170, 250) + 10 = 250 + 10 = 260$ ns.
For $n = 1000$ instructions through a $k = 5$ -stage pipeline with no stalls, the total number of clock cycles is $k + (n - 1) = 5 + 999 = 1004$ cycles.
Total time $= 1004 \times 260 ns = 261040$ ns.
Converting to microseconds: $261040 ns = 261.04 μ s$ .

KEY IDEA

In a synchronous pipeline, the clock cycle time must be long enough for the slowest stage plus the inter-stage latch overhead: $T_{c l k} = max (stage delays) + t_{l a t c h}$ . For $n$ instructions through a $k$ -stage pipeline with no stalls, the total number of cycles is $k + (n - 1)$ (fill the pipeline in $k$ cycles for the first instruction, then one more cycle per remaining instruction).

WATCH OUT FOR

A common error is using $n \times k$ cycles (as if every instruction needed all $k$ cycles independently) instead of the correct $k + (n - 1)$ pipelined cycle count, or forgetting to add the latch delay to the slowest stage when computing the clock period.

From the GATE 2025 CS2 paper. Every question of this paper · Download the full paper · All 12 Pipelining questions, with notes

GATE 2025 CS2 Q.56: solution and answer

Answer and solution

More Pipelining questions