GATE 2023 IN Q.41: solution and answer

GATE 2023 · INQ.41 · 2 marks · MCQ

For the given digital circuit, A = B = 1. Assume that AND, OR, and NOT gates have propagation delays of 10 ns, 10 ns, and 5 ns respectively. All lines have zero propagation delay. Given that C = 1 when the circuit is turned on, the frequency of steady-state oscillation of the output Y is ______.

GATE 2023 IN question 41: Combinational loop. — Figure from the GATE 2023 IN paper. It is part of the question.

(A)
20 MHz
(B)
15 MHz
(C)
40 MHz
(D)
50 MHz

Answer and solution

ANSWER

With $A = B = 1$ the circuit becomes $Y = \overline{C}$ with $C = Y$ : a single inversion around a loop whose delay is $5 + 10 + 10 = 25 ns$ . The period is $2 \times 25 = 50 ns$ , so the output oscillates at $20 MHz$ , option (A).

Official answer: ASource: Official answer key, GATE 2023 IN (IIT Kanpur)

Write the logic. With $\overline{X}$ meaning complement: $Y = A \cdot (\overline{C} + \overline{B})$ . The feedback wire from the output back to the $C$ input makes $C = Y$ .
Put in the constants $A = B = 1$ . Then $\overline{B} = 0$ , so the OR gate passes $\overline{C}$ straight through ( $\overline{C} + 0 = \overline{C}$ ). Because $A = 1$ , the AND gate passes the OR output straight through ( $1 \cdot \overline{C} = \overline{C}$ ). So $Y = \overline{C}$ , but only after a delay.
Since $C = Y$ , the closed path contains exactly one inversion. That makes it a ring oscillator: no stable state is possible, because $Y = \overline{Y}$ has no solution. So $Y$ keeps toggling.
Delay once around the loop, through NOT, then OR, then AND: $t_{l oo p} = 5 + 10 + 10 = 25 ns$ . The NOT gate on $B$ is not in the loop, because $B$ is a constant and that gate's output never changes.
Trace from $C = Y = 1$ at $t = 0$ . The NOT output falls to 0 at $5 ns$ , the OR output at $15 ns$ , and $Y = C$ at $25 ns$ . That new 0 goes round again: the NOT output rises to 1 at $30 ns$ , the OR output at $40 ns$ , and $Y$ at $50 ns$ . So $Y$ stays at each level for $25 ns$ . How the gates power up can affect the first few nanoseconds, but not the steady-state period.
In an inverting loop, the output needs one trip round the loop to go from 1 to 0 and a second trip to go back to 1. So the period is twice the loop delay: $T = 2 t_{l oo p} = 2 \times 25 ns = 50 ns$ .
$f = \frac{1}{T} = \frac{1}{50 ns} = 20 MHz$ This is option (A).

KEY IDEA

A closed loop with an odd number of inversions is a ring oscillator. Its period is twice the total propagation delay round the loop, and only gates whose inputs actually change count towards that delay. Here the constant inputs A and B make the OR and AND gates act as plain delays, so the loop is effectively one inverter plus 20 ns of extra delay.

WATCH OUT FOR

Taking the period as a single trip round the loop gives $25 ns$ and 40 MHz (option C). You need two trips, one for each edge. Counting only the OR and AND delays and missing the NOT gate in the loop gives $20 ns$ , which students often misread as the period and so pick 50 MHz (option D). Adding the NOT gate on $B$ is also wrong: $B$ is constant, so that gate is not in the loop.

From the GATE 2023 IN paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2023 IN Q.41: solution and answer

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