GATE 2023 EC Q.64: solution and answer

GATE 2023 · ECQ.64 · 2 marks · NAT

In the circuit below, the voltage $V_{L}$ is ________ V (rounded off to two decimal places).

GATE 2023 EC question 64: A CMOS current-mirror circuit, supply V_DD on a top rail and ground at the bottom. — Figure from the GATE 2023 EC paper. It is part of the question.

Answer and solution

ANSWER

$V_{L} = 2.00 V$

Official answer: 2.00Source: Official answer key, GATE 2023 EC (IIT Kanpur)

Assumptions. Every transistor is in saturation. Channel-length modulation is neglected ( $λ = 0$ ). All PMOS devices share one $μ_{p} C_{o x}$ and $V_{tp}$ , and all NMOS devices share one $μ_{n} C_{o x}$ and $V_{t n}$ . Every source sits on a supply rail, so there is no body effect. With these assumptions, transistors that share a gate-source voltage carry drain currents in proportion to their $W / L$ : $I_{D} = \frac{1}{2} μ C_{o x} \frac{W}{L} (V_{GS} - V_{t})^{2} \propto \frac{W}{L}$ . The labels $M_{1}$ to $M_{5}$ and node X are not printed on the figure. They are used here only to name the devices.
Reference branch. The diode-connected PMOS $M_{1}$ ( $W / L = 1$ ) carries all of the source current, $I_{R E F} = 1 mA$ . That current fixes the $V_{S G}$ shared by $M_{1}$ , $M_{2}$ and $M_{3}$ . $M_{1}$ is always saturated because $V_{S D} = V_{S G} > V_{S G} - ∣ V_{tp} ∣$ .
PMOS mirror (equal $V_{S G}$ , so $I_{D} \propto W / L$ ). $I_{D 2} = \frac{10}{1} (1 mA) = 10 mA$ and $I_{D 3} = \frac{7}{1} (1 mA) = 7 mA$ .
Second reference. Node X has only one other path, so all 10 mA from $M_{2}$ flows into the diode-connected NMOS $M_{4}$ ( $W / L = 10$ ). This sets the $V_{GS}$ that $M_{4}$ and $M_{5}$ share.
NMOS mirror. $I_{D 5} = \frac{5}{10} (10 mA) = 5 mA$ . $M_{5}$ draws this current out of the $V_{L}$ node and sends it to ground.
KCL at the output node. $M_{3}$ pushes 7 mA into the node and $M_{5}$ pulls 5 mA out. The only other path is the load, so the difference goes through it to ground: $I_{L} = 7 - 5 = 2 mA$ .
Ohm's law. $V_{L} = I_{L} R_{L} = (2 mA) (1 k Ω) = 2.00 V$ This answer holds only if $M_{3}$ and $M_{5}$ stay saturated with their drains at 2 V. $V_{D D}$ and the thresholds are not given, so the question intends ideal mirror operation, and that is assumed here.

KEY IDEA

This is a cascade of current mirrors. When transistors share a gate-source voltage and are in saturation with $λ = 0$ , their drain currents scale with $W / L$ . The PMOS mirror multiplies the 1 mA reference to 10 mA and 7 mA. The NMOS mirror then scales the 10 mA to 5 mA. KCL at the output node leaves $7 - 5 = 2 mA$ for the 1 kΩ load.

WATCH OUT FOR

There are three common slips. The first is taking the NMOS ratio against the 1 mA source instead of the 10 mA branch, which gives $I_{D 5} = 5/1 \times 1 = 5$ mA by luck or $5/10 \times 1 = 0.5$ mA by mistake. The second is scaling the current through $M_{5}$ from $M_{3}$ 's 7 mA, when $M_{5}$ is mirrored from $M_{4}$ 's branch. The third is adding the two currents at the output node (12 mA, so 12 V) when $M_{3}$ sources current into the node and $M_{5}$ sinks current out of it.

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GATE 2023 EC Q.64: solution and answer

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