GATE 2023 EC Q.21: solution and answer

Official answer: DSource: Official answer key, GATE 2023 EC (IIT Kanpur)

1. Identify the devices. The top PMOS has its source at $V_{DD}$ and its gate at the DC bias $V_1$. Both are AC ground, so it has no small-signal drive. Seen from its drain, it is just its output resistance $r_{op}$, an active (current-source) load. The bottom NMOS has its gate at the DC bias $V_2$, so its gate is at AC ground. The signal enters at its source and leaves at its drain, so the NMOS is a common-gate stage. The source $v_{IN}$ in series with $R_1$ is the signal source together with its own resistance. Its Norton equivalent is a current $v_{IN}/R_1$ in parallel with $R_1$. So the amplifier's input port is the NMOS source and its output port is the drain node $v_{OUT}$.

2. Small-signal model and assumptions. Each MOSFET is modelled as $g_m{v}_{gs}$ with $r_o$ from drain to source. Body effect is neglected, and we take $g_m{r}_{on}\gg 1$. The NMOS gate is at AC ground, so $v_{gs}=-v_s$.

3. Input resistance, looking into the NMOS source. Apply a test voltage $v_x$ at the source and let $i_x$ flow in. The gate draws no current, so $i_x$ leaves through the drain into $r_{op}$, which gives $v_d=i_x{r}_{op}$. The current through the NMOS from source to drain is $$i_x=g_m{v}_x+\frac{v_x-v_d}{r_{on}}=g_m{v}_x+\frac{v_x}{r_{on}}-\frac{i_x{r}_{op}}{r_{on}}$$ Solving for $v_x/i_x$: $$R_{in}=\frac{r_{on}+r_{op}}{1+g_m{r}_{on}}\approx \frac{1}{g_m}\left(1+\frac{r_{op}}{r_{on}}\right)$$ With $r_{op}$ comparable to $r_{on}$, $R_{in}\approx 2/g_m$. That is of the order of $1/g_m$, so the input impedance is low.

4. Output resistance, looking into the drain node. Set $v_{IN}=0$, so the NMOS source goes to ground through $R_1$. Apply $v_x$ at the drain and let $i_x$ flow into the NMOS drain. Then $v_s=i_x{R}_1$ and $v_{gs}=-i_x{R}_1$, so $$i_x=-g_m{i}_x{R}_1+\frac{v_x-i_x{R}_1}{r_{on}}\Rightarrow R_{down}=r_{on}+R_1+g_m{r}_{on}{R}_1\approx r_{on}(1+g_m{R}_1)$$ Looking up, you see the PMOS resistance $r_{op}$. So $$R_{out}=r_{op}\parallel r_{on}(1+g_m{R}_1)$$ This is of the order of $r_o$, so the output impedance is high.

5. Transfer. The gate draws no current, so the current entering the NMOS source is exactly the current leaving its drain: $i_d=i_s$. $R_{in}$ is much smaller than the source resistance $R_1$, so almost all of the Norton current $v_{IN}/R_1$ goes into the source: $i_{in}\approx v_{IN}/R_1$. With the output shorted to AC ground, $r_{op}$ carries no current and $i_{out}=i_{in}$. The short-circuit current gain is $1$, so the stage is a current buffer.

6. Classify. Each ideal controlled source has fixed port impedances. VCVS: $Z_{in}\to \infty$, $Z_{out}\to 0$. VCCS: $Z_{in}\to \infty$, $Z_{out}\to \infty$. CCVS: $Z_{in}\to 0$, $Z_{out}\to 0$. CCCS: $Z_{in}\to 0$, $Z_{out}\to \infty$. This circuit has a low $Z_{in}$ (about $1/g_m$) and a high $Z_{out}$ (about $r_o$), which matches the current-controlled current source, option (D).