GATE 2025 EC Q.35: solution and answer

GATE 2025 · ECQ.35 · 1 mark · NAT

A 4-bit weighted-resistor DAC with inputs $b_{3}$ , $b_{2}$ , $b_{1}$ , and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic '1' and open otherwise.

When the input $b_{3} b_{2} b_{1} b_{0}$ changes from 1110 to 1101, the magnitude of the change in the output voltage $V_{O}$ (in mV, rounded off to the nearest integer) is ________.

GATE 2025 EC question 35: A reference source V_REF = 2 V drives a common top rail. — Figure from the GATE 2025 EC paper. It is part of the question.

Answer and solution

ANSWER

The output changes from $- 3.5 V$ to $- 3.25 V$ , so the magnitude of the change in $V_{O}$ is $250 mV$ .

Official answer: 250Source: Official answer key, GATE 2025 EC (IIT Roorkee)

The op-amp is ideal and its + input is grounded, so the − input is a virtual ground ( $0 V$ ). A closed switch on bit $b_{i}$ carries $I_{i} = \frac{V _{R E F}}{R _{i}}$ into that node. An open switch carries no current.
Total current into the summing node: $I = V_{R E F} (\frac{b _{3}}{R} + \frac{b _{2}}{2 R} + \frac{b _{1}}{4 R} + \frac{b _{0}}{8 R})$
No current enters an ideal op-amp input, so all of $I$ flows through the feedback resistor $R_{f} = R$ . This is an inverting summing amplifier: $V_{O} = - I R_{f} = - V_{R E F} (b_{3} + \frac{b _{2}}{2} + \frac{b _{1}}{4} + \frac{b _{0}}{8}) = - 2 (b_{3} + \frac{b _{2}}{2} + \frac{b _{1}}{4} + \frac{b _{0}}{8}) V$
For $b_{3} b_{2} b_{1} b_{0} = 1110$ : $V_{O} = - 2 (1 + 0.5 + 0.25) = - 3.5 V$ .
For $b_{3} b_{2} b_{1} b_{0} = 1101$ : $V_{O} = - 2 (1 + 0.5 + 0.125) = - 3.25 V$ .
Magnitude of the change: $∣Δ V_{O} ∣ = ∣ - 3.25 - (- 3.5) ∣ = 0.25 V = 250 mV$ .
Check using the step size. One LSB is $V_{R E F} \cdot \frac{R _{f}}{8 R} = \frac{2}{8} = 0.25 V$ . The input code drops from $(1110)_{2} = 14$ to $(1101)_{2} = 13$ , which is exactly one LSB, so $∣Δ V_{O} ∣ = 1 \times 250 mV = 250 mV$ .

KEY IDEA

In a weighted-resistor DAC with a virtual-ground summing node, $V_{O} = - V_{R E F} \frac{R _{f}}{R} (b_{3} + \frac{b _{2}}{2} + \frac{b _{1}}{4} + \frac{b _{0}}{8})$ . The output is proportional to the binary value of the input code, so any change in output equals (change in code) $\times$ (one LSB step). Here one LSB is $V_{R E F} R_{f} / (8 R) = 0.25 V$ , and $14 \to 13$ is a change of one step.

WATCH OUT FOR

Two bits flip ( $b_{1}$ : $1 \to 0$ , $b_{0}$ : $0 \to 1$ ), and a common error is to add the two contributions as magnitudes ( $0.5 + 0.25 = 0.75 V$ ) when they have opposite signs and partly cancel, leaving a net $0.25 V$ . Two other slips: pairing the LSB $b_{0}$ with the smallest resistor $R$ instead of $8 R$ , which reverses the bit weights, and taking the step as $V_{R E F} / 2^{4} = 0.125 V$ as if this were an R-2R ladder with full-scale $V_{R E F}$ . In this circuit the feedback resistor equals the MSB resistor, so the MSB alone gives $V_{R E F}$ and the LSB step is $V_{R E F} /8$ .

From the GATE 2025 EC paper. Every question of this paper · Download the full paper · All 18 ADC & DAC questions, with notes

GATE 2025 EC Q.35: solution and answer

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