Memories and microprocessors

Semiconductor memory is classified by what happens at power-off. Volatile memory (SRAM, DRAM) loses its contents; non-volatile memory (the ROM family) keeps them. Random access means every location is reached in the same time whatever its address. SRAM and DRAM are read/write random-access memories; ROMs are random-access too, but in common usage RAM means read/write memory.

Conventions used throughout these notes: positive logic; an overline marks an active-low signal (for example $\overline{\text{CS}}$ selects a chip when it is 0) and also the complement of a bit; address and data bits are numbered MSB first, $A_{15}$ down to $A_0$ on a 16-bit bus; signed numbers are 2's complement.

SRAM: the 6T cell. Two cross-coupled CMOS inverters (four transistors) form a latch holding $Q$ and $\overline{Q}$. Two access transistors, gated by the word line WL, connect $Q$ and $\overline{Q}$ to the bit lines BL and $\overline{\text{BL}}$.

Read: both bit lines are precharged high, WL is raised, and the side storing 0 pulls its bit line slightly low; a differential sense amplifier resolves the bit. The stored value is not lost. Write: write drivers force BL and $\overline{\text{BL}}$ to opposite levels, overpowering the latch. Hold: with WL low the latch keeps its state for as long as power is applied. No refresh is needed; that is what static means.

DRAM: the 1T1C cell. One access transistor connects a storage capacitor $C_S$ to the bit line when the word line is high; the bit is the charge on $C_S$.

Read: the bit line is precharged (commonly to $V_{DD}/2$), the word line is raised, and charge sharing between $C_S$ and the much larger bit-line capacitance $C_{BL}$ shifts the bit line by a small $\Delta V$, which a sense amplifier amplifies. Charge sharing destroys the stored level, so the sense amplifier writes the value back (restore): a DRAM read is destructive.

Leakage: the stored charge leaks away, so every row must be read and restored (refreshed) once in every refresh period $T_{\text{ref}}$, whether it is accessed or not. Opening a row refreshes every cell in that row together.

Addressing: to save pins, the row address and then the column address are sent on the same pins, latched by $\overline{\text{RAS}}$ and $\overline{\text{CAS}}$.

Cycle time: after each access the row must be restored and the bit lines precharged again, so a DRAM's cycle time (the minimum interval between successive accesses) is longer than its access time.

A chip organised as $2^n\times m$ holds $2^n$ words of $m$ bits. It has $n$ address lines $A_{n-1}\dots A_0$, $m$ data lines, and active-low controls: chip select $\overline{\text{CS}}$, output enable $\overline{\text{OE}}$ (read) and write enable $\overline{\text{WE}}$. In memory sizes $1\text{K}=2^{10}$ and $1\text{M}=2^{20}$; a size written with B (such as 16 KB) is in bytes, while a size written as $W\times m$ is W words of m bits.

Width (word-size) expansion: chips placed side by side share every address line and the same chip select; each drives its own slice of the data bus (two $4\text{K}\times 4$ chips make $4\text{K}\times 8$).

Depth (word-count) expansion: banks share the low address lines and the data bus; a decoder driven by the higher address lines enables exactly one bank at a time. A general design uses both.

Full (absolute) decoding uses every upper address line, so each location has exactly one address. Partial decoding leaves some upper lines unconnected to save logic; each location then responds at several addresses (fold-back or mirror images). Partial decoding is acceptable only if no image overlaps another device.

A machine instruction is a binary word with an opcode field (the operation) and operand fields (register numbers, memory addresses or constants). Instruction groups are data transfer, arithmetic and logic, branch and control, and input/output. The number of explicit addresses gives the instruction format: more addresses per instruction means fewer instructions per program but longer instructions.

The addressing mode tells the processor how to find the operand or its effective address (EA). Notation: A = the address or displacement field of the instruction, R = a register, M[x] = contents of memory location x. The memory-reference column counts the accesses needed to obtain the operand after the instruction itself has been fetched.

The ALU is a combinational block: an adder with input conditioning performs add, subtract (as $A+\overline{B}+1$), increment, decrement and compare; a logic unit performs AND, OR, XOR and NOT; a shifter performs shifts and rotates. A function-select code from the control unit chooses the operation. The ALU also produces status flags: carry C (carry or borrow out of the MSB, meaningful for unsigned numbers), zero Z, sign S (the MSB of the result), overflow V (signed overflow) and parity P.

The datapath is the ALU together with the registers and buses that feed it: program counter PC, instruction register IR, memory address register MAR, memory data register MDR, the general-purpose registers and the flag register. The control unit issues, in every clock period, the control signals (register load enables, bus and multiplexer selects, ALU function, memory read/write) that make the datapath perform one step of the instruction cycle. On a single internal bus only one register can drive the bus in a step, which is why a fetch takes several steps.

Horizontal microinstructions have one bit per control signal: wide words, no decoding, and any combination of signals can be active together. Vertical microinstructions encode each group of mutually exclusive signals (signals never active in the same step) into a short field that is decoded: a narrower control memory, at the cost of decoding delay and less parallelism. In the format used in these notes, each microinstruction also carries sequencing information: a condition-select field (which flag to test) and a next-address field (the branch target in control memory).

Pipelining splits instruction processing into $k$ stages separated by latches (pipeline registers), so $k$ instructions are in progress at once, each in a different stage. The classic 5-stage pipeline is IF (instruction fetch), ID (decode and register read), EX (ALU operation or address calculation), MEM (data-memory access) and WB (write back to the register file). All stages share one clock, so its period is set by the slowest stage plus the latch delay. Pipelining does not make one instruction faster; it raises the rate at which instructions complete.

The 8085 at a glance. 8-bit data bus and 16-bit address bus (64 KB memory space). The low address byte and the data share pins $A{D}_7\dots A{D}_0$; an external latch strobed by ALE in the first T-state of each machine cycle holds $A_7\dots A_0$. Registers: accumulator A; general-purpose B, C, D, E, H, L, usable as the 16-bit pairs BC, DE, HL (HL is the memory pointer M); 16-bit stack pointer SP and program counter PC; the flag register with S ($D_7$), Z ($D_6$), AC ($D_4$), P ($D_2$) and CY ($D_0$). Multi-byte values are stored low byte first: in a 3-byte instruction the second byte is the low-order byte of the address or data (LDA 2050H is stored as 3A, 50, 20), and a 16-bit word in memory has its low byte at the lower address. The stack grows toward lower addresses and SP points to the last byte stored: PUSH rp stores the high-order register at SP − 1 and the low-order register at SP − 2, then SP ← SP − 2; POP reverses this and adds 2 to SP; CALL pushes the return address (the address of the instruction after the CALL). Control and status pins include $\text{IO}/\overline{\text{M}}$, $\overline{\text{RD}}$, $\overline{\text{WR}}$, ALE, READY (inserts wait states for slow devices) and HOLD/HLDA (for DMA).

An instruction takes one or more machine cycles: opcode fetch takes 4 T-states (6 for some, such as INX, DCX, PUSH and CALL); memory read, memory write, I/O read and I/O write take 3 T-states each. One T-state is one clock period.

Memory and I/O interfacing. Memory chips connect as in the memory-organisation section: low address lines to the chip, upper lines to the select decoder, data bus in parallel. The 8085's $\text{IO}/\overline{\text{M}}$ tells a memory cycle ($\text{IO}/\overline{\text{M}}=0$) from an I/O cycle (1), and simple gates combine it with $\overline{\text{RD}}$ and $\overline{\text{WR}}$ into four separate active-low strobes.

Programmable peripheral interface (8255). Three 8-bit ports A, B, C and a control register, selected by $A_1{A}_0$ = 00, 01, 10, 11. In the I/O-mode control word $D_7=1$; $D_6{D}_5$ = mode of group A (port A and upper port C), $D_4$ = port A, $D_3$ = upper port C, $D_2$ = mode of group B (port B and lower port C), $D_1$ = port B, $D_0$ = lower port C, where 1 = input and 0 = output. Mode 0 is simple I/O, mode 1 is handshake (strobed) I/O, mode 2 is bidirectional (port A only). All ports as mode-0 outputs is 80H; port A as input with the rest as outputs is 90H. $D_7=0$ selects the bit set/reset mode for single port-C bits.

Interrupts. The 8085 checks its interrupt inputs during the last machine cycle of each instruction, so a request is serviced only after the current instruction completes. On accepting one it resets the interrupt-enable flip-flop (as DI would), pushes the PC (the return address) onto the stack and jumps to a vector address; the service routine re-enables with EI if required and ends with RET. EI and DI enable and disable all maskable interrupts; SIM sets the individual masks of RST 7.5, 6.5 and 5.5, and RIM reads them. TRAP is unaffected by EI, DI and SIM. The one-byte software instruction RST n (n = 0 to 7) acts as a CALL to its vector.

Data-transfer schemes. Programmed (polled) I/O: the CPU repeatedly reads a status bit; simple but wasteful. Interrupt-driven I/O: the device signals when ready and the CPU runs a service routine. DMA: a DMA controller requests the buses (HOLD), the CPU releases them and acknowledges (HLDA), and data moves between memory and the device without passing through the CPU; used for fast block transfers.

The 8051 microcontroller (classic version). An 8-bit CPU with 4 KB of on-chip program ROM, 128 bytes of RAM, four 8-bit I/O ports P0 to P3 (32 lines), two 16-bit timer/counters, a full-duplex serial port and five interrupt sources (external INT0 and INT1, timer 0, timer 1, serial). Program and data have separate 64 KB address spaces. Internal RAM: four register banks R0 to R7 at 00H–1FH (chosen by RS1, RS0 in the PSW), a bit-addressable area at 20H–2FH, general scratch RAM at 30H–7FH; the special function registers sit at 80H–FFH. SP resets to 07H and the stack grows upward.

An embedded system is a computer built into a larger product to do a dedicated job: a microcontroller or microprocessor with memory, I/O and firmware, usually under tight limits on cost, power and memory, and often under real-time constraints. In a hard real-time task a missed deadline is a failure; in a soft real-time task it only degrades the result.

Virtual instrumentation replaces a fixed-function bench instrument with general-purpose data acquisition hardware plus software on a computer. The software decides what the instrument is (oscilloscope, spectrum analyser, data logger), presents a software front panel of controls and indicators, and is changed by reprogramming rather than by new hardware. Graphical dataflow programming, in which a block diagram of wired function blocks is the program, is widely used for it.

The Internet of Things connects sensing and actuating devices to networks so their data can be collected, analysed and acted on remotely. Protocols designed for constrained devices: MQTT, publish-subscribe through a broker over TCP with very small headers; CoAP, request-response in the style of HTTP (GET, PUT, POST, DELETE) over UDP. Edge computing processes data near the devices to cut latency and bandwidth, leaving storage and heavy analysis to the cloud.