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GATE 2023 EC Q.63: solution and answer

GATE 2023 · ECQ.63 · 2 marks · NAT

In a given sequential circuit, initial states are and . For a clock frequency of , the frequency of signal in kHz, is ________ (rounded off to the nearest integer).

GATE 2023 EC question 63: Two positive-edge-triggered D flip-flops (clock input shown as a plain triangle with no bubble) share one clock, labelled…Tap to open full size
Figure from the GATE 2023 EC paper. It is part of the question.
Figure description

Two positive-edge-triggered D flip-flops (clock input shown as a plain triangle with no bubble) share one clock, labelled CLK = 1 MHz. Flip-flop 1 has input D_1 and outputs Q_1 and Q_1. Flip-flop 2 has input D_2 and outputs Q_2 and Q_2. A feedback wire runs from the Q_2 output, up over the top of both flip-flops, and down into D_1, so D_1 = Q_2. A diagonal wire joins the Q_1 output (with its bubble) to D_2, so D_2 = Q_1. The Q_1 output and the Q_2 output are short stubs that connect to nothing else. This is a 2-bit twisted-ring (Johnson) counter.

Answer and solution

ANSWER

The circuit cycles through the four states , so repeats every 4 clock periods and .

Official answer: 250, or 500Source: Official answer key, GATE 2023 EC (IIT Kanpur)

  1. Read the connections from the figure: (the feedback wire over the top) and (the diagonal wire from the bubbled output; the bar marks the complement). The and outputs are unused stubs. Both flip-flops take the same clock, so they change state together on each clock edge.

  2. D flip-flop characteristic equation: . So and .

  3. Step the state forward from the given start . Clock 1: , , giving .

  4. Clock 2: , , giving . Clock 3: , , giving . Clock 4: , , giving , which is the starting state again.

  5. The sequence repeats every 4 clock pulses. The loop through the two flip-flops has exactly one inversion, so this is a 2-bit twisted-ring (Johnson) counter, which has states for .

  6. Over one cycle reads . That is a square wave (50% duty cycle) whose period is 4 clock periods.

KEY IDEA

Write for each flip-flop and step the state table from the given initial state until it repeats. The number of states in the cycle is the division ratio: an output that repeats every clocks has frequency . A shift loop with exactly one inversion (a twisted-ring, or Johnson, counter) of flip-flops has states, so here .

WATCH OUT FOR

Reading the diagonal wire as coming from instead of . With no inversion the loop is a plain ring counter, , which gives a 2-state cycle and 500 kHz. (The official key accepts both 250 and 500, but the figure as printed gives 250.) A second slip is to count state changes of rather than full periods: changes every 2 clocks, but one full period is 4 clocks.

From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

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