Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is ________.
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Two D flip-flops, FF1 (left) and FF2 (right), both driven by a common CLK line. FF1 has its D input pin drawn on its right side and its Q output on its lower-left side. FF2 has its Q output on its left side and its D input on its right side. Node A (top-left terminal) is tied by a wire running down to FF1's Q output, so A = Q_1. A drives both inputs of a two-input NOR gate (both inputs shorted together, so the NOR acts as an inverter); the NOR output is node B. B and node C are the two inputs of a two-input X-OR gate whose output is node D (top-right terminal). Node D is wired down to the D input of FF2. FF2's Q output is wired left to the D input of FF1, and a junction on that wire goes up to node C, so C = Q_2 = D_1. So: A = Q_1, B = A (NOR of A with A), C = Q_2, D = B C, D_1 = Q_2, D_2 = D.