GATE 2023 IN Q.60: solution and answer

GATE 2023 · INQ.60 · 2 marks · NAT

In the circuit shown, the input voltage $V_{in} = 100 mV$ . The switch and the opamp are ideal. At time $t = 0$ , the initial charge stored in the $10 nF$ capacitor is $1 nC$ , with the polarity as indicated in the figure. The switch S is controlled using a $1 kHz$ square-wave voltage signal $V_{s}$ as shown. Whenever $V_{s}$ is 'High', S is in position '1' and when $V_{s}$ is 'Low', S is in position '2'.

At $t = 20 ms$ , the magnitude of the voltage $V_{o}$ will be ________ mV (rounded off to the nearest integer).

GATE 2023 IN question 60: Switched-capacitor integrator. — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

ANSWER

$V_{o} (20 ms) = - 100 mV$ , so the magnitude of $V_{o}$ is $100 mV$ .

Official answer: 99 to 101Source: Official answer key, GATE 2023 IN (IIT Kanpur)

Assumptions. Ideal op-amp: infinite gain, no input current, and the output stays in its linear range (it only swings about $\pm 100 mV$ here). Ideal switch and ideal source: the 1 nF capacitor charges or discharges instantly when S changes position. Write $C_{1} = 1 nF$ and $C_{f} = 10 nF$ .
Initial output (virtual ground). The feedback capacitor holds $Q_{0} = 1 nC$ , so $V_{C_{f}} = \frac{1 nC}{10 nF} = 100 mV$ . Its '+' plate is on the output side and its '−' plate on the inverting-input side. The non-inverting input is grounded, so the inverting input is a virtual ground at $0 V$ , which gives $V_{o} (0) = + 100 mV$ .
Timing. $f = 1 kHz \Rightarrow T = 1 ms$ . The waveform starts High at $t = 0$ , so in every period S is at '1' for the first $0.5 ms$ and at '2' for the next $0.5 ms$ .
Phase 1 (S at '1'). $C_{1}$ is connected straight across $V_{in}$ and charges to $q = C_{1} V_{in} = 1 nF \times 100 mV = 0.1 nC$ , with the top plate positive. Any charge $C_{1}$ held before $t = 0$ does not matter, because the first thing that happens is this connection to $V_{in}$ . During this phase $C_{1}$ is not connected to the op-amp, so $V_{o}$ holds its value.
Phase 2 (S at '2'). The top plate of $C_{1}$ is now tied to the virtual ground at $0 V$ , so $C_{1}$ discharges completely. Its $0.1 nC$ flows into the inverting node. The op-amp draws no input current, so all of this charge lands on the inverting-input ('−') plate of $C_{f}$ .
Change per period (charge conservation at the inverting node). Adding $+ 0.1 nC$ to the '−' plate, which carried $- 1 nC$ , leaves $- 0.9 nC$ on it. So every transfer lowers the output by $Δ V_{o} = - \frac{C _{1} V _{in}}{C _{f}} = - \frac{0.1 nC}{10 nF} = - 10 mV per clock period$
Count the transfers. With an ideal switch, each transfer happens the moment S moves to '2', at $t = 0.5, 1.5, 2.5, \dots, 19.5 ms$ . That is $N = 20$ transfers by $t = 20 ms$ . At $t = 20 ms$ S moves back to '1', which disconnects $C_{1}$ from the op-amp and leaves $V_{o}$ unchanged.
Result. $V_{o} (20 ms) = 100 mV - 20 \times 10 mV = - 100 mV$ The magnitude is $∣ V_{o} ∣ = 100 mV$ .
Check with the equivalent resistor. A switched capacitor behaves like $R_{e q} = \frac{1}{f C _{1}} = \frac{1}{( 1 0 ^{3} ) ( 1 0 ^{- 9} )} = 1 M Ω$ . The average input current is $\frac{100 mV}{1 M Ω} = 0.1 μ A$ , which delivers $2 nC$ in $20 ms$ (exactly 20 whole periods). So $Δ V_{o} = - \frac{2 nC}{10 nF} = - 200 mV$ and $V_{o} = 100 - 200 = - 100 mV$ , which agrees.

KEY IDEA

This circuit is a switched-capacitor inverting integrator. In every clock period the 1 nF capacitor picks up $C_{1} V_{in}$ from the input and dumps it at the virtual ground, onto the feedback capacitor, so the output steps by $- \frac{C _{1}}{C _{f}} V_{in} = - 10 mV$ each period. The 1 nC starting charge fixes the starting point: because the inverting input is a virtual ground, $V_{o} (0) = + Q_{0} / C_{f} = + 100 mV$ . After 20 periods, $V_{o} = 100 - 200 = - 100 mV$ .

WATCH OUT FOR

1. Ignoring the 1 nC initial charge. That gives $∣ V_{o} ∣ = 200 mV$ .
2. Reading the polarity backwards, so $V_{o} (0) = - 100 mV$ . That gives $- 300 mV$ , a magnitude of $300 mV$ .
3. Treating the stage as non-inverting and adding the steps: $100 + 200 = 300 mV$ .
4. Counting 19 or 40 transfers instead of 20. There is exactly one charge transfer per 1 ms period, at each High-to-Low edge.

From the GATE 2023 IN paper. Every question of this paper · Download the full paper · All 36 Op-amps questions, with notes

GATE 2023 IN Q.60: solution and answer

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