GATE EC · EE · IN

Op-amp circuits

Characteristics, applications and compensation

Op-amp circuits use negative feedback to turn a very high-gain differential amplifier into amplifiers, summers, integrators, converters, precision rectifiers and log amplifiers. Their behaviour is set only by the external components, through the virtual short that the feedback creates. To solve these questions you apply that short correctly with KCL at the inverting node, recognise when it does not hold, and correct the ideal result for finite gain, gain-bandwidth product, slew rate, offsets and CMRR. EC candidates also need dominant-pole (Miller) compensation and phase margin.

36 previous-year questions · 36 solved · 6 practice questions

The ideal op-amp, the virtual short and the node method

An op-amp amplifies the difference between its two inputs: $v_{o} = A (v_{+} - v_{-})$ . Unless a finite value is given, these notes use the ideal op-amp: open-loop gain $A \to \infty$ , input resistance $R_{i} \to \infty$ (no current into either input), output resistance $R_{o} = 0$ , infinite bandwidth and slew rate, zero offset voltage and bias current, and infinite CMRR. The output can swing only between $\pm V_{s a t}$ , just inside the supply rails.

OPEN-LOOP RELATION AND VIRTUAL SHORT

v_{o} = A (v_{+} - v_{-}), v_{+} - v_{-} = \frac{v _{o}}{A} \to 0 as A \to \infty

The input difference goes to zero only when negative feedback holds the output at a finite value inside $\pm V_{s a t}$ .

With negative feedback the output settles wherever it has to so that $v_{-} = v_{+}$ . This is the virtual short. It is an equality of voltages only: no current flows between the inputs. When $v_{+}$ is grounded, $v_{-}$ sits at 0 V and is called a virtual ground. Because $R_{o} = 0$ , the output can source or sink whatever current the circuit demands. KCL at the op-amp output node therefore only brings in the op-amp's own output current as an extra unknown, so do not use it to find $v_{o}$ ; write KCL at the inverting node instead.

Node method for any linear op-amp circuit

Check that the net feedback goes to the inverting input. If it does not, stop: the virtual short does not apply.
Find $v_{+}$ from the network on the non-inverting side. No current enters the input, so a plain voltage divider (or weighted average) gives it. If that network is also connected to $v_{o}$ , keep $v_{o}$ in the expression.
Set $v_{-} = v_{+}$ .
Write KCL at the inverting node with zero current into the op-amp.
Solve for $v_{o}$ . With several sources, superposition works because the circuit is linear.

When the virtual short does NOT hold

Situation	What happens	How to analyse
Open loop (comparator)	Output is $+ V_{s a t}$ if $v_{+} > v_{-}$ and $- V_{s a t}$ if $v_{+} < v_{-}$	Compare the two input voltages directly
Positive feedback only (Schmitt trigger, astable)	Output latches at $\pm V_{s a t}$ ; $v_{+} \neq = v_{-}$ except at the switching instant	Find $v_{+}$ for each output state; the output switches when $v_{-}$ crosses it
Negative feedback but output saturated (overdriven amplifier, integrator at a rail, simple super diode on its off half-cycle)	The loop is broken, so the inputs are no longer equal	Treat the output as a fixed $\pm V_{s a t}$ source
Output slewing	The output cannot follow; $v_{+} - v_{-}$ is large during the edge	The output changes at the slew rate
Both positive and negative feedback	The net sign decides	With resistive networks the virtual short holds only if the fraction of $v_{o}$ returned to $v_{-}$ exceeds the fraction returned to $v_{+}$

EXAM TIP

The feedback current enters the inverting node through the feedback element and then has nowhere to go but the other elements at that node, because the op-amp input draws nothing. Load current is supplied by the op-amp output and never appears in the inverting-node equation.

Linear amplifiers: inverting, non-inverting, summer, difference and instrumentation

Convention: $R_{1}$ runs from the input (or ground) to the inverting node and $R_{f}$ from the output to the inverting node. $β = R_{1} / (R_{1} + R_{f})$ is the feedback factor, and $1/ β = 1 + R_{f} / R_{1}$ is the noise gain. It is the noise gain, not the signal gain, that later sets the bandwidth and multiplies the input offset voltage.

INVERTING AMPLIFIER

\frac{v _{o}}{v _{i}} = - \frac{R _{f}}{R _{1}}, R_{in} = R_{1}, R_{o u t} = 0

The input goes through $R_{1}$ to the virtual-ground node, so the source sees only $R_{1}$ .

NON-INVERTING AMPLIFIER AND VOLTAGE FOLLOWER

\frac{v _{o}}{v _{i}} = 1 + \frac{R _{f}}{R _{1}}, R_{in} \to \infty

The input is at $v_{+}$ , with $R_{1}$ from $v_{-}$ to ground. The gain is never below 1. With $R_{f} = 0$ or $R_{1} \to \infty$ this is the voltage follower, $v_{o} = v_{i}$ , used as a buffer.

INVERTING SUMMER

v_{o} = - R_{f} (\frac{v _{1}}{R _{1}} + \frac{v _{2}}{R _{2}} + \dots + \frac{v _{n}}{R _{n}})

Each input sees only its own resistor because the summing node is a virtual ground, so the inputs do not interact. With all resistors equal, $v_{o} = - (v_{1} + \dots + v_{n})$ .

NON-INVERTING SUMMER

v_{+} = \frac{\sum _{k} v _{k} / R _{k}}{\sum _{k} 1/ R _{k}}, v_{o} = (1 + \frac{R _{f}}{R _{g}}) v_{+}

The inputs go through $R_{k}$ to $v_{+}$ (with no other resistor at $v_{+}$ ), which settles at their conductance-weighted average; $R_{g}$ runs from $v_{-}$ to ground. Here the inputs do interact: changing one $R_{k}$ changes every weight.

DIFFERENCE AMPLIFIER (GENERAL)

v_{o} = - \frac{R _{2}}{R _{1}} v_{1} + (1 + \frac{R _{2}}{R _{1}}) \frac{R _{4}}{R _{3} + R _{4}} v_{2}

$v_{1}$ goes through $R_{1}$ to $v_{-}$ , with $R_{2}$ from the output to $v_{-}$ ; $v_{2}$ goes through $R_{3}$ to $v_{+}$ , with $R_{4}$ from $v_{+}$ to ground. The result follows by superposition.

BALANCED DIFFERENCE AMPLIFIER

\frac{R _{4}}{R _{3}} = \frac{R _{2}}{R _{1}} \Rightarrow v_{o} = \frac{R _{2}}{R _{1}} (v_{2} - v_{1})

The common-mode input cancels only with this ratio match. The differential input resistance is $2 R_{1}$ when $R_{3} = R_{1}$ and $R_{4} = R_{2}$ ; $v_{2}$ alone sees $R_{3} + R_{4}$ .

DIFFERENCE AMPLIFIER WITH RESISTOR MISMATCH (IDEAL OP-AMP)

A_{c m} = \frac{R _{1} R _{4} - R _{2} R _{3}}{R _{1} ( R _{3} + R _{4} )}, A_{d} = \frac{1}{2} [\frac{R _{2}}{R _{1}} + \frac{( R _{1} + R _{2} ) R _{4}}{R _{1} ( R _{3} + R _{4} )}]

Here $v_{d} = v_{2} - v_{1}$ and $v_{c m} = (v_{1} + v_{2}) /2$ . Any mismatch makes $A_{c m} \neq = 0$ , so resistor tolerance alone can limit the CMRR of this circuit even with a perfect op-amp.

The three-op-amp instrumentation amplifier puts a non-inverting buffer on each input, so neither input draws current, and follows them with a balanced difference amplifier. In the first stage, op-amp A1 (input $v_{1}$ at its $v_{+}$ ) and op-amp A2 (input $v_{2}$ ) each have a resistor $R$ from output to inverting input, and a single gain resistor $R_{G}$ joins the two inverting inputs. The virtual shorts put $v_{2} - v_{1}$ across $R_{G}$ , so the current $(v_{2} - v_{1}) / R_{G}$ flows through $R$ , $R_{G}$ and $R$ in series. The differential voltage is therefore amplified by $1 + 2 R / R_{G}$ . A common-mode voltage appears unchanged at both outputs, because no current flows in $R_{G}$ . The second stage (input resistors $R_{3}$ , feedback and ground resistors $R_{4}$ ) amplifies $v_{o 2} - v_{o 1}$ .

THREE-OP-AMP INSTRUMENTATION AMPLIFIER

v_{o} = (1 + \frac{2 R}{R _{G}}) \frac{R _{4}}{R _{3}} (v_{2} - v_{1})

$v_{2}$ drives the op-amp whose output feeds the non-inverting side of the difference stage. The gain is set by the single resistor $R_{G}$ without disturbing the matched $R_{3}$ and $R_{4}$ . The first-stage outputs are $v_{o 1} = v_{1} - R (v_{2} - v_{1}) / R_{G}$ and $v_{o 2} = v_{2} + R (v_{2} - v_{1}) / R_{G}$ .

CURRENT-TO-VOLTAGE AND VOLTAGE-TO-CURRENT CONVERTERS

I-to-V: v_{o} = - i_{s} R_{f}, V-to-I (load Z_{L} in place of R_{f}): i_{L} = \frac{v _{i}}{R _{1}}

I-to-V (transimpedance) converter: the source current $i_{s}$ flows into the virtual-ground node and all of it goes through $R_{f}$ , so the source sees zero resistance. V-to-I converter with a floating load: the load replaces $R_{f}$ in an inverting amplifier, so the current $v_{i} / R_{1}$ flows through it from the inverting node towards the output whatever $Z_{L}$ is, as long as the output $v_{o} = - i_{L} Z_{L}$ stays inside $\pm V_{s a t}$ .

Linear configurations at a glance (ideal op-amp)

Circuit	Ideal gain	Resistance seen by the source	Noise gain $1/ β$
Inverting	$- R_{f} / R_{1}$	$R_{1}$	$1 + R_{f} / R_{1}$
Non-inverting	$1 + R_{f} / R_{1}$	$\infty$	$1 + R_{f} / R_{1}$
Voltage follower	$1$	$\infty$	$1$
Inverting summer, $n$ inputs	$- R_{f} / R_{k}$ per input	$R_{k}$ per input	$1 + R_{f} / (R_{1} ∥ \dots ∥ R_{n})$
Balanced difference	$R_{2} / R_{1}$ on $(v_{2} - v_{1})$	$2 R_{1}$ differential (with $R_{3} = R_{1}$ , $R_{4} = R_{2}$ )	$1 + R_{2} / R_{1}$
Instrumentation	$(1 + 2 R / R_{G}) (R_{4} / R_{3})$	$\infty$ at both inputs	—

EXAM TIP

An inverting amplifier with gain $- 1$ still has a noise gain of 2. In the inverting and non-inverting forms alike, the noise gain $1 + R_{f} / R_{1}$ multiplies $V_{O S}$ , and $f_{t}$ divided by the noise gain is the closed-loop bandwidth.

EXAM TIP

In the instrumentation amplifier with ideal first-stage op-amps, the first stage amplifies the difference by $1 + 2 R / R_{G}$ but passes the common-mode signal at unity gain, even if its two $R$ resistors are not matched. The overall CMRR is therefore $(1 + 2 R / R_{G})$ times the CMRR of the difference stage alone.

Integrator and differentiator

Replace $R_{f}$ in the inverting amplifier with a capacitor $C$ , and the input current $v_{i} / R$ has nowhere to go but into $C$ : the output is the negative running integral of the input. Swap the positions of $R$ and $C$ and the output becomes the negative derivative. Both results follow from the inverting-gain formula written with impedances, $H = - Z_{f} / Z_{1}$ .

IDEAL INVERTING INTEGRATOR

v_{o} (t) = - \frac{1}{R C} \int_{0}^{t} v_{i} (τ) d τ + v_{o} (0), H (j ω) = - \frac{1}{j ω R C}

$∣ H ∣ = 1$ at $ω = 1/ (R C)$ and falls at 20 dB/decade. The phase is $+ 9 0^{\circ}$ (the output leads the input). The DC gain is infinite.

PRACTICAL INTEGRATOR (RF ACROSS C)

H (j ω) = - \frac{R _{f} / R}{1 + j ω R _{f} C}

It integrates only for $f ≫ f_{c} = 1/ (2 π R_{f} C)$ . Below $f_{c}$ it is an inverting amplifier of gain $- R_{f} / R$ , which stops offsets and bias currents from ramping the output into saturation.

INTEGRATOR WITH FINITE OPEN-LOOP GAIN A

H (j ω) = - \frac{A}{1 + j ω ( 1 + A ) R C}

The op-amp is ideal except for a frequency-independent gain $A$ . The DC gain is $- A$ instead of infinite, and the pole sits at $ω = 1/ [(1 + A) R C]$ , because $C$ appears at the inverting node multiplied by $(1 + A)$ (the Miller effect). Well above that pole the circuit integrates, and as $A \to \infty$ it reduces to $- 1/ (j ω R C)$ .

IDEAL DIFFERENTIATOR

v_{o} (t) = - R C \frac{d v _{i}}{d t}, H (j ω) = - j ω R C

$∣ H ∣ = 1$ at $ω = 1/ (R C)$ , and the gain rises at 20 dB/decade without limit. The phase is $- 9 0^{\circ}$ (the output lags the input).

PRACTICAL DIFFERENTIATOR (R1 IN SERIES WITH C)

H (j ω) = - \frac{j ω R C}{1 + j ω R _{1} C}

It differentiates only for $f ≪ 1/ (2 π R_{1} C)$ , and the high-frequency gain is capped at $- R / R_{1}$ . A small capacitor across $R$ is sometimes added to roll the gain off further.

INTEGRATOR OUTPUT FOR A SQUARE-WAVE INPUT

Δ v_{o, pp} = \frac{V _{m} T}{2 R C}

For a zero-average square wave of $\pm V_{m}$ and period $T$ , the output slopes at $\mp V_{m} / (R C)$ for $T /2$ each half-cycle. A practical integrator needs $R_{f} C ≫ T$ for this to hold.

Standard input-output pairs (ideal circuits; for the sine, the steady-state output with the integration constant dropped)

Input	Integrator output	Differentiator output
Step of height $V$	Ramp of slope $- V / (R C)$ until saturation	Impulse $- R C V δ (t)$ (in practice a spike clipped at the rail), then 0
Square wave $\pm V_{m}$ , period $T$	Triangle, peak-to-peak $V_{m} T / (2 R C)$	Spikes of alternating sign at each edge
Triangle of slopes $\pm S$	Piecewise parabola (close to a sine)	Square wave: $- R C S$ while the input rises, $+ R C S$ while it falls
$V_{m} sin ω t$	$\frac{V _{m}}{ω R C} cos ω t$ , amplitude $\propto 1/ f$	$- ω R C V_{m} cos ω t$ , amplitude $\propto f$

WORKED EXAMPLE

A practical inverting integrator uses $R = 10 k Ω$ , $C = 0.1 μ F$ and $R_{f} = 1 M Ω$ across $C$ . The input is a zero-average square wave of $\pm 1$ V at 1 kHz. The op-amp is ideal except for an input offset voltage $V_{O S} = 2$ mV. Find (a) the peak-to-peak output, (b) the DC level of the output, and (c) what happens if $R_{f}$ is removed.

Solution

Check that the circuit integrates at 1 kHz: $f_{c} = \frac{1}{2 π R _{f} C} = \frac{1}{2 π ( 1 0 ^{6} ) ( 1 0 ^{- 7} )} = 1.59$ Hz, far below 1 kHz, and $R_{f} C = 0.1$ s is much greater than $T = 1$ ms.
$R C = (1 0^{4}) (1 0^{- 7}) = 1$ ms. During each half-period $T /2 = 0.5$ ms the output slopes at $V_{m} / (R C) = 1$ V/ms.
(a) $Δ v_{o, pp} = \frac{V _{m} T}{2 R C} = \frac{( 1 ) ( 1 0 ^{- 3} )}{2 ( 1 0 ^{- 3} )} = 0.5$ V. The output is a triangle, falling while the input is $+ 1$ V and rising while it is $- 1$ V.
(b) At DC the capacitor is open, so the circuit is an inverting amplifier with $R_{f} / R = 100$ and noise gain $1 + R_{f} / R = 101$ . The output offset is $101 \times 2 mV = 0.202$ V, and the triangle rides on this level (its sign follows the sign of $V_{O S}$ ).
(c) Without $R_{f}$ the DC gain is infinite. With $v_{+} = v_{-} = V_{O S}$ , a constant current of magnitude $V_{O S} / R = 0.2 μ$ A flows in $R$ and therefore through $C$ , so $v_{o} = V_{O S} + \frac{V _{O S}}{R C} t$ . The output drifts at 2 V/s; taking the saturation level as 12 V, it saturates in about 6 s.

Answer: (a) A 0.5 V peak-to-peak triangle. (b) It rides on a DC level of about 0.2 V. (c) Without Rf the output drifts at 2 V/s until it saturates (about 6 s for a 12 V saturation level).

EXAM TIP

Sign check: both circuits invert. For $v_{i} = V_{m} sin ω t$ the integrator gives $+ \frac{V _{m}}{ω R C} cos ω t$ (the two minus signs cancel) and the differentiator gives $- ω R C V_{m} cos ω t$ .

EXAM TIP

Why the ideal forms fail in practice. The ideal integrator's infinite DC gain integrates $V_{O S}$ and the bias current until the output saturates. The ideal differentiator's rising gain amplifies high-frequency noise, and its RC feedback network adds a pole to the loop that, together with the op-amp's own pole, leaves little phase margin, so the output rings. $R_{f}$ in the integrator and $R_{1}$ in the differentiator are the cures.

Precision rectifiers, log and antilog amplifiers

A diode on its own cannot rectify a signal smaller than its cut-in voltage $V_{γ}$ . Putting the diode inside the feedback loop divides that dead zone by the open-loop gain. The diodes here can be ideal or constant-drop (0.7 V): either way the op-amp removes the drop from the output.

SUPER DIODE (DIODE INSIDE THE LOOP)

V_{γ, eff} = \frac{V _{γ}}{A}

$A$ is the op-amp's open-loop gain. The op-amp output drives the diode anode. The cathode is the output node, which has a load resistor to ground and is fed back to $v_{-}$ ; $v_{i}$ is at $v_{+}$ . The output is $v_{o} = v_{i}$ for $v_{i} > 0$ and $v_{o} = 0$ (pulled down by the load) for $v_{i} < 0$ . On the negative half the loop is open and the op-amp saturates at $- V_{s a t}$ , so it recovers slowly at high frequency.

The improved (inverting) precision half-wave rectifier adds a second diode so that the op-amp never saturates. It has input resistor $R_{1}$ and feedback resistor $R_{2}$ . Diode $D_{1}$ runs from $v_{-}$ (anode) to the op-amp output (cathode). Diode $D_{2}$ runs from the op-amp output (anode) to the output node, and $R_{2}$ connects the output node back to $v_{-}$ . For $v_{i} > 0$ the op-amp output goes negative, $D_{1}$ conducts and clamps it one diode drop below ground, $D_{2}$ is off, and the output node is held at the virtual ground through $R_{2}$ . For $v_{i} < 0$ , $D_{2}$ conducts and the circuit is an inverting amplifier.

IMPROVED PRECISION HALF-WAVE RECTIFIER (DIODES AS DESCRIBED)

v_{o} = ⎩ ⎨ ⎧ - \frac{R _{2}}{R _{1}} v_{i}, 0, v_{i} < 0 v_{i} > 0

Reversing both diodes passes the other half-cycle: $v_{o} = - (R_{2} / R_{1}) v_{i}$ for $v_{i} > 0$ and 0 otherwise. The op-amp output stays within about one diode drop of ground (while $D_{1}$ conducts) or of the output node (while $D_{2}$ conducts), so it never saturates and there is no saturation recovery.

The precision full-wave rectifier (absolute-value circuit) takes a half-wave rectifier of gain $- 1$ that passes the positive half ( $v_{A} = - v_{i}$ for $v_{i} > 0$ , otherwise 0; diodes reversed from the circuit above) and follows it with an inverting summer that weights $v_{i}$ by 1 and $v_{A}$ by 2 (input resistors $R$ and $R /2$ , feedback resistor $R$ ).

PRECISION FULL-WAVE RECTIFIER

v_{o} = - (v_{i} + 2 v_{A}) = ∣ v_{i} ∣

For $v_{i} > 0$ : $v_{A} = - v_{i}$ , so $v_{o} = - (v_{i} - 2 v_{i}) = v_{i}$ . For $v_{i} < 0$ : $v_{A} = 0$ , so $v_{o} = - v_{i}$ . Reversing both diodes gives $- ∣ v_{i} ∣$ .

A log amplifier puts a diode (or a BJT with its base grounded) in the feedback path. It uses the exponential diode law $i_{D} = I_{S} e^{v_{D} / V_{T}}$ (the $- 1$ term neglected, ideality factor 1), with $V_{T} = 25$ mV at room temperature unless stated. With the diode's anode at $v_{-}$ and an input resistor $R$ , the input current $v_{i} / R$ flows through the diode and forces $v_{D} = - v_{o}$ . Swapping $R$ and the diode gives the antilog (exponential) amplifier.

LOG AMPLIFIER

v_{o} = - V_{T} ln (\frac{v _{i}}{I _{S} R}), v_{i} > 0

It works for one input polarity only (reverse the diode for $v_{i} < 0$ ). The output depends on temperature through both $V_{T}$ and $I_{S}$ . With a BJT (collector at $v_{-}$ , base grounded, emitter at the output), $I_{S}$ is the transistor's saturation current.

ANTILOG AMPLIFIER

v_{o} = - I_{S} R e^{v_{i} / V_{T}}, v_{i} > 0

The diode (anode at the input) is in series with the input, and $R$ is in the feedback path.

LOG AMPLIFIER SLOPE

Δ v_{o} = - V_{T} ln 10 \approx - 57.6 mV per decade of v_{i} (V_{T} = 25 mV)

At $V_{T} = 26$ mV it is $- 59.9$ mV per decade. Only the ratio of the two inputs matters, so $I_{S}$ and $R$ cancel: $v_{o 2} - v_{o 1} = - V_{T} ln (v_{i 2} / v_{i 1})$ .

EXAM TIP

Log amplifiers on two inputs, followed by a summer and then an antilog amplifier, give an output proportional to $v_{1} v_{2}$ . Subtracting the logs instead gives division. Track the sign and the scale factor through every inverting stage.

Non-idealities: finite gain, bandwidth, slew rate, offsets and CMRR

A real op-amp has finite gain that falls with frequency, a maximum output slope, and small DC errors at its inputs. Keep the small-signal limits (gain and bandwidth, which apply at any amplitude) separate from the large-signal limit (slew rate, which depends on amplitude).

CLOSED-LOOP GAIN WITH FINITE OPEN-LOOP GAIN (NON-INVERTING)

G = \frac{A}{1 + A β} = \frac{1}{β} \cdot \frac{A β}{1 + A β}, β = \frac{R _{1}}{R _{1} + R _{f}}

The op-amp is ideal except for its finite gain $A$ ( $R_{i} \to \infty$ , $R_{o} = 0$ ). $A β$ is the loop gain. As $A \to \infty$ , $G \to 1/ β = 1 + R_{f} / R_{1}$ .

CLOSED-LOOP GAIN WITH FINITE OPEN-LOOP GAIN (INVERTING)

G = \frac{- R _{f} / R _{1}}{1 + \frac{1 + R _{f} / R _{1}}{A}}

The loop gain is the same $A β$ with the same $β = R_{1} / (R_{1} + R_{f})$ . The virtual ground now sits at $- v_{o} / A$ rather than exactly 0.

FRACTIONAL GAIN ERROR

ε = \frac{G _{ideal} - G}{G _{ideal}} = \frac{1}{1 + A β} \approx \frac{1 + R _{f} / R _{1}}{A}

This holds for both configurations; the approximation needs $A β ≫ 1$ . A higher closed-loop gain means a smaller loop gain and a larger error.

INPUT AND OUTPUT RESISTANCE WITH FINITE GAIN

non-inverting: R_{in} \approx R_{i} (1 + A β), R_{o u t} \approx \frac{R _{o}}{1 + A β}; inverting: R_{in} \approx R_{1} + \frac{R _{f}}{1 + A}

$R_{i}$ is the op-amp's differential input resistance and $R_{o}$ its open-loop output resistance, with $β = R_{1} / (R_{1} + R_{f})$ . The approximations need $R_{i} ≫ R_{1} ∥ R_{f}$ and $R_{o}$ much smaller than $R_{1} + R_{f}$ and the load. The output-resistance result also holds for the inverting amplifier, with the same $β$ . In the inverting amplifier (taking $R_{i} \to \infty$ , $R_{o} = 0$ ), the resistance looking into the inverting node is $R_{f} / (1 + A)$ , which is why that node behaves as a virtual ground.

INTERNALLY COMPENSATED OP-AMP (SINGLE POLE)

A (j ω) = \frac{A _{0}}{1 + j ω / ω _{b}}, ω_{t} = A_{0} ω_{b}

$ω_{b}$ is the open-loop 3-dB frequency. For $A_{0} ≫ 1$ , $f_{t} = A_{0} f_{b}$ is the unity-gain frequency, also called the gain-bandwidth product (GBW). For $ω ≫ ω_{b}$ , $∣ A ∣ \approx ω_{t} / ω$ .

CLOSED-LOOP BANDWIDTH

f_{3 dB} = f_{b} (1 + A_{0} β) \approx β f_{t} = \frac{f _{t}}{1 + R _{f} / R _{1}}

This is the same for inverting and non-inverting amplifiers built with the same resistors: the bandwidth is $f_{t}$ divided by the noise gain.

GAIN-BANDWIDTH PRODUCT IN EACH CONFIGURATION

non-inverting: G_{0} f_{3 dB} = f_{t}, inverting: \frac{R _{f}}{R _{1}} f_{3 dB} = \frac{R _{f} / R _{1}}{1 + R _{f} / R _{1}} f_{t}

An inverting amplifier of gain $- 1$ has a bandwidth of $f_{t} /2$ , not $f_{t}$ .

N IDENTICAL SINGLE-POLE STAGES IN CASCADE

f_{3 dB,total} = f_{1} 2^{1/ n} - 1

Each stage has bandwidth $f_{1}$ and the stages do not load each other. Two stages give $0.644 f_{1}$ ; three give $0.510 f_{1}$ .

SMALL-SIGNAL RISE TIME (10% TO 90%)

t_{r} = 2.2 τ = \frac{2.2}{2 π f _{3 dB}} \approx \frac{0.35}{f _{3 dB}}

Applies to a single-pole closed-loop response to a small step.

SLEW RATE

S R = \frac{d v _{o}}{d t}_{m a x}, ω V_{p} \leq S R for an undistorted sine V_{p} sin ω t

This is a large-signal limit on the output and does not depend on the closed-loop gain. A heavily slew-limited sine approaches a triangle, and a large step becomes a ramp of slope SR.

FULL-POWER BANDWIDTH

f_{M} = \frac{S R}{2 π V _{o, m a x}}

The highest frequency at which a sine at the full rated output amplitude $V_{o, m a x}$ is undistorted. Above $f_{M}$ the amplitude must drop to $S R / (2 π f)$ .

EXAM TIP

Step response: if the output of a single-pole closed loop would step by $V$ (the input step times the closed-loop gain), its initial slope is $V ω_{3 dB}$ . If $V ω_{3 dB} \leq S R$ , the edge is exponential with $τ = 1/ ω_{3 dB}$ ; otherwise it starts as a slew-limited ramp of slope SR. For a sine, the usable frequency is the lower of the small-signal bandwidth and $S R / (2 π V_{p})$ .

WORKED EXAMPLE

A non-inverting amplifier has $R_{1} = 1 k Ω$ and $R_{f} = 19 k Ω$ . The op-amp has $A_{0} = 2 \times 1 0^{5}$ , a single pole with $f_{t} = 1$ MHz, and $S R = 0.5 V / μ s$ . Find (a) the exact DC closed-loop gain and its error, (b) the 3-dB bandwidth and the small-signal rise time, (c) the largest undistorted output sine amplitude at 20 kHz, and (d) the full-power bandwidth for a 10 V peak output.

Solution

$β = \frac{R _{1}}{R _{1} + R _{f}} = \frac{1}{20}$ , so the ideal gain is 20 and the loop gain is $A_{0} β = 1 0^{4}$ .
(a) $G = \frac{A _{0}}{1 + A _{0} β} = \frac{2 \times 1 0 ^{5}}{10001} = 19.998$ . The error is $\frac{1}{1 + A _{0} β} \approx 1 0^{- 4}$ , i.e. 0.01%.
(b) $f_{3 dB} = β f_{t} = \frac{1 MHz}{20} = 50$ kHz, and $t_{r} = \frac{0.35}{50 kHz} = 7 μ$ s.
(c) Slew limit: $2 π f V_{p} \leq S R \Rightarrow V_{p} \leq \frac{0.5 \times 1 0 ^{6}}{2 π ( 2 \times 1 0 ^{4} )} = 3.98$ V. At 20 kHz the small-signal gain is still $20/ 1 + (20/50)^{2} = 18.6$ , so for any output above about 4 V it is the slew rate, not the bandwidth, that sets the limit.
(d) $f_{M} = \frac{S R}{2 π V _{o, m a x}} = \frac{0.5 \times 1 0 ^{6}}{2 π ( 10 )} = 7.96$ kHz.

Answer: (a) 19.998, an error of 0.01%. (b) 50 kHz and 7 µs. (c) 3.98 V peak. (d) 7.96 kHz.

DC errors. Model the input offset voltage $V_{O S}$ as a DC source in series with the non-inverting input of an otherwise ideal op-amp. Model the bias currents $I_{B 1}$ (into $v_{-}$ ) and $I_{B 2}$ (into $v_{+}$ ) as current sources flowing into the input terminals. Then set the signal to zero and find the output. $V_{O S}$ is multiplied by the noise gain in every configuration, because killing the signal source leaves the same circuit either way.

OUTPUT OFFSET DUE TO INPUT OFFSET VOLTAGE

V_{o} = V_{O S} (1 + \frac{R _{f}}{R _{1}})

This is the same for inverting and non-inverting amplifiers. In an integrator without $R_{f}$ , $V_{O S}$ makes the output ramp at $V_{O S} / (R C)$ , and the bias current $I_{B 1}$ makes it ramp at $I_{B 1} / C$ .

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

I_{B} = \frac{I _{B 1} + I _{B 2}}{2}, I_{O S} = ∣ I_{B 1} - I_{B 2} ∣

Here both currents are taken as flowing into the input terminals.

OUTPUT ERROR DUE TO BIAS CURRENTS

V_{o} = I_{B 1} R_{f} (no compensation), V_{o} = R_{f} (I_{B 1} - I_{B 2}) with R_{3} = R_{1} ∥ R_{f} at v_{+}

Signal sources are replaced by their resistances (zero for an ideal source; in the inverting amplifier any source resistance is part of $R_{1}$ ). Without $R_{3}$ the non-inverting input sits at 0 V, so no current flows in $R_{1}$ and all of $I_{B 1}$ flows through $R_{f}$ . Choosing $R_{3} = R_{1} ∥ R_{f}$ makes the two bias currents see equal resistances, which leaves only $∣ V_{o} ∣ = I_{O S} R_{f}$ . $R_{3}$ does nothing about $V_{O S}$ .

WORST-CASE TOTAL OUTPUT OFFSET (WITH BIAS COMPENSATION)

∣ V_{o} ∣_{m a x} = V_{O S} (1 + \frac{R _{f}}{R _{1}}) + I_{O S} R_{f}

The signs of $V_{O S}$ and $I_{O S}$ are unknown for a given device, so the worst case adds the magnitudes.

CMRR. A real op-amp responds slightly to the average of its inputs: $v_{o} = A_{d} v_{d} + A_{c m} v_{c m}$ , with $v_{d} = v_{+} - v_{-}$ and $v_{c m} = (v_{+} + v_{-}) /2$ . The effect is an extra input-referred error of $v_{c m} / CMRR$ . It matters in the non-inverting amplifier and the follower (where $v_{c m} \approx v_{i}$ ) and in the difference amplifier. In the inverting amplifier both inputs stay near ground, so $v_{c m} \approx 0$ .

COMMON-MODE REJECTION RATIO

CMRR = \frac{A _{d}}{A _{c m}}, CMRR_{dB} = 20 lo g_{10} \frac{A _{d}}{A _{c m}}

Applies to the bare op-amp and to a whole difference or instrumentation amplifier. For a circuit, $A_{d}$ and $A_{c m}$ are its gains to $v_{2} - v_{1}$ and to $(v_{1} + v_{2}) /2$ .

PSRR. A change in a supply voltage also shifts the output. The power-supply rejection ratio describes this, but it is quoted in two ways. One is the change in input-referred offset per volt of supply change (for example in µV/V; smaller is better). The other is the ratio of the differential gain to the gain from the supply to the output (usually in dB; larger is better). Check which form a question uses before substituting.

Frequency compensation and phase margin

With feedback, the closed-loop gain is $A / (1 + A β)$ , and the loop gain $L (j ω) = A (j ω) β$ decides stability. If $∠ L$ reaches $- 18 0^{\circ}$ while $∣ L ∣ \geq 1$ , the fed-back signal returns in phase with at least its original size and the amplifier oscillates. (This reading of the Bode plot, and the margins below, assume the usual loop: no right-half-plane poles, and $∣ L ∣$ falls through 1 only once.) An op-amp has at least one pole per gain stage plus higher parasitic poles, so without compensation its phase approaches or passes $- 18 0^{\circ}$ while $∣ A ∣$ is still large. With resistive feedback, $β$ does not depend on frequency, and the worst case is $β = 1$ (the voltage follower), because that is where the loop gain is largest.

PHASE MARGIN

PM = 18 0^{\circ} + ∠ L (j ω_{c}), ∣ L (j ω_{c}) ∣ = 1

$ω_{c}$ is the loop-gain crossover frequency. PM > 0 means the loop is stable. A small PM shows up as peaking in the frequency response and ringing in the step response.

GAIN MARGIN

GM = - 20 lo g_{10} ∣ L (j ω_{180}) ∣ dB, ∠ L (j ω_{180}) = - 18 0^{\circ}

A positive GM (in dB) means the loop is stable.

PHASE MARGIN OF A TWO-POLE LOOP

PM = 9 0^{\circ} - tan^{- 1} (\frac{ω _{c}}{ω _{p 2}}) (ω_{p 1} ≪ ω_{c})

$ω_{c}$ is the true crossover frequency. $ω_{c} = ω_{p 2}$ gives 45°, $ω_{c} = ω_{p 2} / 3$ gives 60°, and $ω_{c} = ω_{p 2} /2$ gives 63.4°.

CLOSED-LOOP DAMPING OF A TWO-POLE LOOP

ω_{n} \approx β ω_{t} ω_{p 2}, ζ \approx \frac{1}{2} \frac{ω _{p 2}}{β ω _{t}}

For $L (s) = β A_{0} / [(1 + s / ω_{p 1}) (1 + s / ω_{p 2})]$ with $ω_{p 1} ≪ ω_{p 2}$ , $β A_{0} ≫ 1$ and $ω_{t} = A_{0} ω_{p 1}$ , the closed loop is second order. $β ω_{t} = ω_{p 2}$ gives $ζ = 0.5$ , PM $= 51. 8^{\circ}$ and a 16.3% step overshoot. $β ω_{t} = ω_{p 2} /2$ gives $ζ = 0.707$ (maximally flat), PM $= 65. 5^{\circ}$ and a 4.3% overshoot. The frequency response peaks for $ζ < 0.707$ .

Dominant-pole compensation makes one pole so low that $∣ L ∣$ falls to 1 (at 20 dB/decade, with only $- 9 0^{\circ}$ of phase) before the next pole arrives. In straight-line terms, the op-amp's unity-gain frequency $f_{t} = A_{0} f_{D}$ is placed at the second pole $f_{p 2}$ for about 45° in a follower, or below it for more margin. The exact crossover is a little lower than the asymptote suggests, because $∣ L ∣$ is already down by $2$ at $f_{p 2}$ ; for $f_{t} = f_{p 2}$ the true PM is about 52°. A higher closed-loop gain (smaller $β$ ) moves the crossover down to about $β f_{t}$ and increases the PM. Adding a brand-new low pole wastes bandwidth. Miller compensation instead moves the existing first pole down and the second pole up.

Miller compensation in a two-stage op-amp. Stage 1 (transconductance $G_{m 1}$ , output resistance $R_{1}$ , node capacitance $C_{1}$ ) drives stage 2, an inverting stage with $G_{m 2}$ , $R_{2}$ and load capacitance $C_{2}$ . Here $R_{1}$ and $R_{2}$ are the stages' output resistances, not the feedback resistors of the earlier sections. The DC gain is $A_{0} = G_{m 1} R_{1} G_{m 2} R_{2}$ . A capacitor $C_{c}$ connected across stage 2 appears at node 1 multiplied by $(1 + G_{m 2} R_{2})$ , which pushes the first pole down. At high frequency, $C_{c}$ ties stage 2's output to its input, making the output a low-impedance node, which pushes the second pole up. This is pole splitting.

MILLER CAPACITANCE AT THE FIRST-STAGE OUTPUT

C_{M} = C_{c} (1 + G_{m 2} R_{2})

Any capacitance bridging an inverting voltage gain $- A_{2}$ appears at the input as $C (1 + A_{2})$ .

DOMINANT POLE WITH MILLER COMPENSATION

ω_{p 1} \approx \frac{1}{R _{1} C _{c} G _{m 2} R _{2}}

Assumes $G_{m 2} R_{2} ≫ 1$ and $C_{c} G_{m 2} R_{2} ≫ C_{1}$ .

UNITY-GAIN FREQUENCY OF A MILLER-COMPENSATED OP-AMP

ω_{t} = A_{0} ω_{p 1} = \frac{G _{m 1}}{C _{c}}

Set only by $C_{c}$ and the input-stage transconductance.

NON-DOMINANT POLE AFTER POLE SPLITTING

ω_{p 2} \approx \frac{G _{m 2} C _{c}}{C _{1} C _{2} + C _{c} ( C _{1} + C _{2} )} \approx \frac{G _{m 2}}{C _{2}}

The second form needs $C_{1} ≪ C_{c}$ and $C_{1} ≪ C_{2}$ . Keeping $ω_{t} \leq ω_{p 2}$ in a follower requires $C_{c} \geq G_{m 1} C_{2} / G_{m 2}$ .

ZERO INTRODUCED BY THE MILLER CAPACITOR

ω_{z} = \frac{G _{m 2}}{C _{c}} (right-half-plane)

A right-half-plane zero raises the gain but adds phase lag, like a pole. It must lie well above $ω_{t}$ or be cancelled, for example with a resistor in series with $C_{c}$ .

SLEW RATE OF A MILLER-COMPENSATED OP-AMP

S R = \frac{I}{C _{c}} = ω_{t} \frac{I}{G _{m 1}}

$I$ is the tail current of the input differential pair, the most current available to charge $C_{c}$ . For a BJT input pair ( $G_{m 1} = I / (2 V_{T})$ ), $S R = 2 V_{T} ω_{t}$ . For a MOSFET input pair ( $G_{m 1} = I / V_{o v}$ ), $S R = V_{o v} ω_{t}$ .

Compensation design order

Take the worst-case feedback factor. For an op-amp that must be stable at unity gain, that is $β = 1$ .
Find the non-dominant pole, $ω_{p 2} \approx G_{m 2} / C_{2}$ .
Choose the crossover frequency for the required PM from $PM = 9 0^{\circ} - tan^{- 1} (ω_{c} / ω_{p 2})$ . With $β = 1$ , set $ω_{t} \approx ω_{c}$ . The true crossover is slightly below $ω_{t}$ , so the PM achieved is slightly higher than designed.
Size the capacitor: $C_{c} = G_{m 1} / ω_{t}$ .
Check that the RHP zero $G_{m 2} / C_{c}$ is far above $ω_{t}$ , and that $S R = I / C_{c}$ meets the large-signal requirement.

EXAM TIP

A capacitive load adds a pole to the loop (the op-amp's output resistance with $C_{L}$ ) and eats phase margin. In the Miller op-amp, $C_{L}$ is part of $C_{2}$ and lowers $ω_{p 2}$ directly.

EXAM TIP

An op-amp compensated for $β = 1$ is stable at every resistive closed-loop gain, at the cost of bandwidth at high gain. A decompensated op-amp (smaller $C_{c}$ , higher $f_{t}$ ) is stable only above a stated minimum closed-loop gain.

PREVIOUS-YEAR QUESTIONS

36 questions from the EC, EE and IN papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2026 · GATE ECE 2025 · GATE ECE 2023 · GATE ECE 2020 · GATE ECE 2018 · GATE EE 2026 · GATE EE 2025 · GATE EE 2024 · GATE EE 2023 · GATE EE 2022 · GATE EE 2020 · GATE EE 2018 · GATE IN 2026 · GATE IN 2025 · GATE IN 2024 · GATE IN 2023 · GATE IN 2022 · GATE IN 2020 · GATE IN 2018

GATE 2026 EC Q.17

GATE 2026 · ECQ.17 · 1 mark · MCQ

The ideal OP-AMP circuit shown in the Figure produces output voltage $V_{o} = x$ when the Switch, S, is open.

Which of the options represents the output voltage when S is closed?

GATE 2026 EC question 17: Non-inverting amplifier using an ideal op-amp. — Figure from the GATE 2026 EC paper. It is part of the question.

(A)
$x$
(B)
$\frac{2}{3} x$
(C)
$\frac{3}{4} x$
(D)
$\frac{1}{2} x$

Answer and solution

GATE 2026 EC Q.17: answer and solution

GATE 2026 EC Q.53

GATE 2026 · ECQ.53 · 2 marks · MCQ

A circuit using an ideal OP-AMP is shown in the Figure.

Which of the following options gives the correct value of the current $I_{X}$ ?

GATE 2026 EC question 53: Ideal op-amp with its non-inverting (+) input grounded. — Figure from the GATE 2026 EC paper. It is part of the question.

(A)
2.0 mA
(B)
1.5 mA
(C)
3.0 mA
(D)
0 mA

Answer and solution

GATE 2026 EC Q.53: answer and solution

GATE 2026 EC Q.62

GATE 2026 · ECQ.62 · 2 marks · NAT

Consider an ideal OP-AMP circuit as shown in the Figure.

The resistances $R_{1} = R_{2} = R_{3} = R_{4} = 50 k Ω$ .

The magnitude of the closed loop gain is ____.

(rounded off to two decimal places)

GATE 2026 EC question 62: Inverting amplifier with a T-network in the feedback path. — Figure from the GATE 2026 EC paper. It is part of the question.

Answer and solution

GATE 2026 EC Q.62: answer and solution

GATE 2026 EE Q.37

GATE 2026 · EEQ.37 · 2 marks · MCQ

In the circuit shown, the open loop gain of the operational amplifier is $A_{0} = 105$ .

What is the voltage gain of the circuit?

(Round off to two decimal places)

GATE 2026 EE question 37: Inverting amplifier. — Figure from the GATE 2026 EE paper. It is part of the question.

(A)
$- 16.67$
(B)
$- 20.00$
(C)
$- 21.00$
(D)
$- 12.67$

Answer and solution

GATE 2026 EE Q.37: answer and solution

GATE 2026 IN Q.45

GATE 2026 · INQ.45 · 2 marks · MCQ

In the circuit shown below, $R$ is $1 k Ω$ and $R_{f}$ is $10 k Ω$ . If $V_{in}$ is $100 mV$ and the op-amps have supply voltages of $\pm 15 V$ , then $V_{o u t}$ is ________ V.

GATE 2026 IN question 45: Two op-amps, one above the other: the input stage of an instrumentation amplifier. — Figure from the GATE 2026 IN paper. It is part of the question.

(A)
$- 15$
(B)
$15$
(C)
$2.1$
(D)
$1.1$

Answer and solution

GATE 2026 IN Q.45: answer and solution

GATE 2025 EC Q.29

GATE 2025 · ECQ.29 · 1 mark · MSQ

Which of the following statements is/are TRUE with respect to an ideal opamp?

(A)
It has an infinite input resistance
(B)
It has an infinite output resistance
(C)
It has an infinite open-loop differential gain
(D)
It has an infinite open-loop common-mode gain

Answer and solution

GATE 2025 EC Q.29: answer and solution

See the question in the paper

Tap to open full size

GATE 2025 EC Q.29: answer and solution

GATE 2025 EE Q.17

GATE 2025 · EEQ.17 · 1 mark · MCQ

Assuming ideal op-amps, the circuit represents a

GATE 2025 EE question 17: Two op-amps, each powered from +V_DD and -V_EE. — Figure from the GATE 2025 EE paper. It is part of the question.

(A)
summing amplifier.
(B)
difference amplifier.
(C)
logarithmic amplifier.
(D)
buffer.

Answer and solution

GATE 2025 EE Q.17: answer and solution

GATE 2025 EE Q.56

GATE 2025 · EEQ.56 · 2 marks · NAT

The op-amps in the following circuit are ideal. The voltage gain of the circuit is ______ (round off to the nearest integer).

GATE 2025 EE question 56: Two ideal op-amps in cascade (a two-op-amp instrumentation/difference amplifier). — Figure from the GATE 2025 EE paper. It is part of the question.

Answer and solution

GATE 2025 EE Q.56: answer and solution

GATE 2025 IN Q.20

GATE 2025 · INQ.20 · 1 mark · MCQ

For the ideal opamp based circuit shown in the figure, the ratio $\frac{V}{I}$ is

GATE 2025 IN question 20: An independent voltage source V (+ on top, − terminal to GND) drives a current I (arrow pointing right, out of the +… — Figure from the GATE 2025 IN paper. It is part of the question.

(A)
$(\frac{R _{3} + R _{4}}{R _{1} + R _{3}}) R_{1}$
(B)
$(\frac{R _{2} + R _{4}}{R _{1} + R _{3}}) R_{3}$
(C)
$R_{1} + R_{3}$
(D)
$R_{3} + R_{4}$

Answer and solution

GATE 2025 IN Q.20: answer and solution

GATE 2025 IN Q.31

GATE 2025 · INQ.31 · 1 mark · MSQ

The circuits mentioned in the following options are realized using ideal opamp. Among these, the circuit(s) performing non-linear operation on the input signal is/are

(A)
Instrumentation amplifier
(B)
Schmitt trigger
(C)
Logarithmic amplifier
(D)
Precision rectifier

Answer and solution

GATE 2025 IN Q.31: answer and solution

See the question in the paper

Tap to open full size

GATE 2025 IN Q.31: answer and solution

GATE 2024 EE Q.61

GATE 2024 · EEQ.61 · 2 marks · NAT

A difference amplifier is shown in the figure. Assume the op-amp to be ideal. The CMRR (in dB) of the difference amplifier is ________ (rounded off to 2 decimal places).

GATE 2024 EE question 61: Single op-amp difference amplifier. — Figure from the GATE 2024 EE paper. It is part of the question.

Answer and solution

GATE 2024 EE Q.61: answer and solution

GATE 2024 IN Q.29

GATE 2024 · INQ.29 · 1 mark · NAT

Consider the readout circuit of a piezoelectric sensor shown in the figure.

When the piezoelectric sensor generates a charge $q_{p}$ , the resulting change in voltage $V_{x}$ is $- 2$ V. Then the corresponding change in the voltage $V_{o u t}$ is ______ V (rounded off to nearest integer).

Note: Assume all components are ideal.

GATE 2024 IN question 29: A charge-amplifier readout circuit. — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.29: answer and solution

GATE 2024 IN Q.41

GATE 2024 · INQ.41 · 2 marks · MCQ

In the figure shown, both the opamps $A_{1}$ and $A_{2}$ are ideal, except that the opamp $A_{1}$ has an offset voltage ( $V_{os}$ ) of 1 mV. For $V_{in} = 0$ V, the values of the output voltages $V_{o u t 1}$ and $V_{o u t 2}$ , respectively, are

GATE 2024 IN question 41: Two op-amps, A1 (upper) and A2 (lower), each powered by +V_CC and -V_EE. — Figure from the GATE 2024 IN paper. It is part of the question.

(A)
3 mV and −1 mV
(B)
1 mV and 0 mV
(C)
1 mV and −1 mV
(D)
2 mV and 0 mV

Answer and solution

GATE 2024 IN Q.41: answer and solution

GATE 2024 IN Q.59

GATE 2024 · INQ.59 · 2 marks · NAT

In the circuit shown, assume the opamp is ideal and the initial charge on the capacitor is zero. The output voltage at time t = 2 ms is ______ V (rounded off to one decimal place).

GATE 2024 IN question 59: Left: a plot of V_in against t. — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.59: answer and solution

GATE 2023 EC Q.39

GATE 2023 · ECQ.39 · 2 marks · MCQ

The $\frac{V _{O U T}}{V _{I N}}$ of the circuit shown below is

GATE 2023 EC question 39: Three op-amps, each powered from V_CC (top rail) and -V_EE (bottom rail). — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
$- \frac{R _{4}}{R _{3}}$
(B)
$\frac{R _{4}}{R _{3}}$
(C)
$1 + \frac{R _{4}}{R _{3}}$
(D)
$1 - \frac{R _{4}}{R _{3}}$

Answer and solution

GATE 2023 EC Q.39: answer and solution

GATE 2023 EE Q.37

GATE 2023 · EEQ.37 · 2 marks · MCQ

Consider the OP AMP based circuit shown in the figure. Ignore the conduction drops of diodes $D_{1}$ and $D_{2}$ . All the components are ideal and the breakdown voltage of the Zener is 5 V. Which of the following statements is true?

GATE 2023 EE question 37: Inverting op-amp circuit. — Figure from the GATE 2023 EE paper. It is part of the question.

(A)
The maximum and minimum values of the output voltage $V_{O}$ are +15 V and -10 V, respectively.
(B)
The maximum and minimum values of the output voltage $V_{O}$ are +5 V and -15 V, respectively.
(C)
The maximum and minimum values of the output voltage $V_{O}$ are +10 V and -5 V, respectively.
(D)
The maximum and minimum values of the output voltage $V_{O}$ are +5 V and -10 V, respectively.

Answer and solution

GATE 2023 EE Q.37: answer and solution

GATE 2023 IN Q.26

GATE 2023 · INQ.26 · 1 mark · NAT

The opamp in the circuit shown is ideal, except that it has an input bias current of 1 nA and an input offset voltage of 10 $μ$ V. The resulting worst-case output voltage will be $\pm$ ______ $μ$ V (rounded off to the nearest integer).

GATE 2023 IN question 26: Inverting-amplifier configuration with no input signal. — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

GATE 2023 IN Q.26: answer and solution

GATE 2023 IN Q.59

GATE 2023 · INQ.59 · 2 marks · NAT

The opamps in the circuit are ideal. The input signals are

$V_{S 1} = 3 + 0.10 sin (300 t) V$ and $V_{S 2} = - 2 + 0.11 sin (300 t) V$ .

The average value of the voltage $V_{O}$ is ______ V (rounded off to two decimal places).

GATE 2023 IN question 59: Two ideal op-amps, one above the other. — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

GATE 2023 IN Q.59: answer and solution

GATE 2023 IN Q.60

GATE 2023 · INQ.60 · 2 marks · NAT

In the circuit shown, the input voltage $V_{in} = 100 mV$ . The switch and the opamp are ideal. At time $t = 0$ , the initial charge stored in the $10 nF$ capacitor is $1 nC$ , with the polarity as indicated in the figure. The switch S is controlled using a $1 kHz$ square-wave voltage signal $V_{s}$ as shown. Whenever $V_{s}$ is 'High', S is in position '1' and when $V_{s}$ is 'Low', S is in position '2'.

At $t = 20 ms$ , the magnitude of the voltage $V_{o}$ will be ________ mV (rounded off to the nearest integer).

GATE 2023 IN question 60: Switched-capacitor integrator. — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

GATE 2023 IN Q.60: answer and solution

GATE 2023 IN Q.62

GATE 2023 · INQ.62 · 2 marks · NAT

In the circuit shown, assuming an ideal opamp, the value of the output voltage $V_{o}$ = ____ V (rounded off to one decimal place).

GATE 2023 IN question 62: Op-amp with inverting (−) input on top and non-inverting (+) input below; — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

GATE 2023 IN Q.62: answer and solution

GATE 2022 EE Q.16

GATE 2022 · EEQ.16 · 1 mark · MCQ

The steady state output ( $V_{o u t}$ ), of the circuit shown below, will

GATE 2022 EE question 16: Op-amp circuit powered from +V_DD (top) and -V_EE (bottom). — Figure from the GATE 2022 EE paper. It is part of the question.

(A)
saturate to $+ V_{D D}$
(B)
saturate to $- V_{E E}$
(C)
become equal to $0.1 V$
(D)
become equal to $- 0.1 V$

Answer and solution

GATE 2022 EE Q.16: answer and solution

GATE 2022 EE Q.36

GATE 2022 · EEQ.36 · 2 marks · MCQ

The output impedance of a non-ideal operational amplifier is denoted by $Z_{out}$ . The variation in the magnitude of $Z_{out}$ with increasing frequency, $f$ , in the circuit shown below, is best represented by

GATE 2022 EE question 36: Op-amp voltage follower (unity-gain buffer). — Figure from the GATE 2022 EE paper. It is part of the question.

(A)
Figure — $lo g (∣ Z_{out} ∣)$ vs $lo g (f)$ : a horizontal line, constant at all frequencies.
(B)
Figure — $lo g (∣ Z_{out} ∣)$ vs $lo g (f)$ : a straight line rising from the origin, increasing at all frequencies.
(C)
Figure — $lo g (∣ Z_{out} ∣)$ vs $lo g (f)$ : flat at a low level, then a rising straight segment, then flat again at a higher level.
(D)
Figure — $lo g (∣ Z_{out} ∣)$ vs $lo g (f)$ : flat at a high level, then a falling straight segment, then flat again at a lower level.

Answer and solution

GATE 2022 EE Q.36: answer and solution

GATE 2022 EE Q.44

GATE 2022 · EEQ.44 · 2 marks · MCQ

Q.44 The current gain $(I_{o u t} / I_{in})$ in the circuit with an ideal current amplifier given below is

GATE 2022 EE question 44: An ideal op-amp (gain marked ∞). — Figure from the GATE 2022 EE paper. It is part of the question.

(A)
$\frac{C _{f}}{C _{c}}$
(B)
$\frac{- C _{f}}{C _{c}}$
(C)
$\frac{C _{c}}{C _{f}}$
(D)
$\frac{- C _{c}}{C _{f}}$

Answer and solution

GATE 2022 EE Q.44: answer and solution

GATE 2022 IN Q.35

GATE 2022 · INQ.35 · 1 mark · NAT

An OPAMP has a gain of $1 0^{4}$ , an input impedance of $10 M Ω$ and an output impedance of $100 Ω$ . The OPAMP is used in unity-gain feedback configuration in a voltage buffer circuit. The closed-loop output impedance of the OPAMP (in milliohms) in the circuit is ________ (round off to one decimal place)

Answer and solution

GATE 2022 IN Q.35: answer and solution

See the question in the paper

Tap to open full size

GATE 2022 IN Q.35: answer and solution

GATE 2020 EC Q.18

GATE 2020 · ECQ.18 · 1 mark · NAT

In the circuit shown below, all the components are ideal. If $V_{i}$ is $+ 2 V$ , the current $I_{o}$ sourced by the op-amp is ________ mA.

GATE 2020 EC question 18: Non-inverting op-amp amplifier. — Figure from the GATE 2020 EC paper. It is part of the question.

Answer and solution

GATE 2020 EC Q.18: answer and solution

GATE 2020 EE Q.53

GATE 2020 · EEQ.53 · 2 marks · NAT

The temperature of the coolant oil bath for a transformer is monitored using the circuit shown. It contains a thermistor with a temperature-dependent resistance, $R_{t h er mi s t or} = 2 (1 + α T) k Ω$ , where $T$ is the temperature in $^{\circ} C$ . The temperature coefficient, $α$ , is $- (4 \pm 0.25) % /^{\circ} C$ . Circuit parameters: $R_{1} = 1 k Ω$ , $R_{2} = 1.3 k Ω$ , $R_{3} = 2.6 k Ω$ . The error in the output signal (in V, rounded off to 2 decimal places) at $15 0^{\circ} C$ is ________.

GATE 2020 EE question 53: Op-amp circuit. — Figure from the GATE 2020 EE paper. It is part of the question.

Answer and solution

GATE 2020 EE Q.53: answer and solution

GATE 2020 IN Q.17

GATE 2020 · INQ.17 · 1 mark · NAT

Assuming ideal opamps, the output voltage at $V_{1}$ in the figure shown (in volts) is ____

GATE 2020 IN question 17: Two op-amps. — Figure from the GATE 2020 IN paper. It is part of the question.

Answer and solution

GATE 2020 IN Q.17: answer and solution

GATE 2020 IN Q.21

GATE 2020 · INQ.21 · 1 mark · NAT

Assume that the opamp in the circuit shown is ideal.

The value of $\frac{V _{x}}{I _{x}}$ (in $k Ω$ ) is ____

GATE 2020 IN question 21: An op-amp with its non-inverting (+) input on top and its inverting (−) input below; — Figure from the GATE 2020 IN paper. It is part of the question.

Answer and solution

GATE 2020 IN Q.21: answer and solution

GATE 2020 IN Q.38

GATE 2020 · INQ.38 · 2 marks · NAT

Assuming that the opamp used in the circuit shown is ideal, the reading of the 1 Hz bandwidth, permanent magnet moving coil (PMMC) type voltmeter (in volts) is ____

GATE 2020 IN question 38: Inverting precision half-wave rectifier. — Figure from the GATE 2020 IN paper. It is part of the question.

Answer and solution

GATE 2020 IN Q.38: answer and solution

GATE 2020 IN Q.39

GATE 2020 · INQ.39 · 2 marks · NAT

If the opamps in the circuit shown are ideal and $V_{X} = 0.5 mV$ , the steady state value of $V_{O}$ (in volts, rounded off to two decimal places) is ____

GATE 2020 IN question 39: Two ideal op-amps in cascade. — Figure from the GATE 2020 IN paper. It is part of the question.

Answer and solution

GATE 2020 IN Q.39: answer and solution

GATE 2020 IN Q.44

GATE 2020 · INQ.44 · 2 marks · NAT

The circuit shown uses ideal opamp powered from a supply $V_{C C} = 5 V$ . If the charge $q_{p}$ generated by the piezoelectric sensor is of the form $q_{p} = 0.1 sin (10000 π t) μ C$ , the peak detector output after 10 cycles of $q_{p}$ (in volts, rounded off to one decimal place) is ____

GATE 2020 IN question 44: Charge-amplifier circuit. — Figure from the GATE 2020 IN paper. It is part of the question.

Answer and solution

GATE 2020 IN Q.44: answer and solution

GATE 2018 EC Q.2

GATE 2018 · ECQ.2 · 1 mark · MCQ

In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5 volts. At the input, unit step voltage is applied, i.e. $v_{I N} (t) = u (t)$ volts. Also, at $t = 0$ , the voltage across each of the capacitors is zero.

The time $t$ , in milliseconds, at which the output voltage $v_{O U T}$ crosses $- 10 V$ is

GATE 2018 EC question 2: Inverting integrator-type circuit with an ideal op-amp. — Figure from the GATE 2018 EC paper. It is part of the question.

(A)
2.5
(B)
5
(C)
7.5
(D)
10

Answer and solution

GATE 2018 EC Q.2: answer and solution

GATE 2018 EC Q.38

GATE 2018 · ECQ.38 · 2 marks · NAT

Q.38 An op-amp based circuit is implemented as shown below.

[Figure]

In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place) at node A, connected to the negative input of the op-amp as indicated in the figure is ________.

GATE 2018 EC question 38: An inverting amplifier. — Figure from the GATE 2018 EC paper. It is part of the question.

Answer and solution

GATE 2018 EC Q.38: answer and solution

GATE 2018 EE Q.15

GATE 2018 · EEQ.15 · 1 mark · MCQ

The op-amp shown in the figure is ideal. The input impedance $\frac{v _{in}}{i _{in}}$ is given by

GATE 2018 EE question 15: An ideal op-amp with its non-inverting (+) input at the top and its inverting (-) input at the bottom; — Figure from the GATE 2018 EE paper. It is part of the question.

(A)
$Z \frac{R _{1}}{R _{2}}$
(B)
$- Z \frac{R _{2}}{R _{1}}$
(C)
$Z$
(D)
$- Z \frac{R _{1}}{R _{1} + R _{2}}$

Answer and solution

GATE 2018 EE Q.15: answer and solution

GATE 2018 IN Q.41

GATE 2018 · INQ.41 · 2 marks · NAT

An opamp that is powered from a $\pm 5 V$ supply is used to build a non-inverting amplifier having a gain of 15. The slew rate of the opamp is $0.5 \times 1 0^{6} V/s$ . For a sinusoidal input with amplitude of $0.3 V$ , the maximum frequency (in kHz) up to which it can be operated without any distortion is (up to one decimal place) ____.

Answer and solution

GATE 2018 IN Q.41: answer and solution

See the question in the paper

Tap to open full size

GATE 2018 IN Q.41: answer and solution

GATE 2018 IN Q.42

GATE 2018 · INQ.42 · 2 marks · NAT

The circuit given uses ideal opamps. The current $I$ (in $μ$ A) drawn from the source $v_{s}$ is (up to two decimal places) ____.

GATE 2018 IN question 42: A source v_s = 1 V drives a node; — Figure from the GATE 2018 IN paper. It is part of the question.

Answer and solution

GATE 2018 IN Q.42: answer and solution

PRACTICE

6 questions to test yourself

PRACTICE 11 mark · NAT

An inverting amplifier with $R_{1} = 2 k Ω$ and $R_{f} = 18 k Ω$ uses an op-amp with a single-pole open-loop response, DC gain $1 0^{5}$ and unity-gain frequency $f_{t} = 1$ MHz. The closed-loop 3-dB bandwidth, in kHz, is ______.

Answer and solution

Answer: $100$ (accepted range $\pm 0.5$ )

Feedback factor: $β = \frac{R _{1}}{R _{1} + R _{f}} = \frac{2}{20} = 0.1$ . The noise gain is 10, even though the signal gain is $- 9$ .
$f_{b} = f_{t} / A_{0} = 10$ Hz, so $f_{3 dB} = f_{b} (1 + A_{0} β) = 10 \times 10001 \approx 100$ kHz, which equals $β f_{t}$ .
Dividing by the signal gain instead (1 MHz / 9 = 111 kHz) is the trap: the bandwidth of an inverting amplifier is $f_{t}$ divided by $1 + R_{f} / R_{1}$ .

PRACTICE 22 marks · NAT

A difference amplifier uses an ideal op-amp. $v_{1}$ is applied through $R_{1} = 10 k Ω$ to the inverting input, with $R_{2} = 100 k Ω$ from the output to the inverting input. $v_{2}$ is applied through $R_{3} = 10 k Ω$ to the non-inverting input, with $R_{4} = 101 k Ω$ from the non-inverting input to ground. Taking $v_{d} = v_{2} - v_{1}$ and $v_{c m} = (v_{1} + v_{2}) /2$ , the CMRR of the circuit, in dB, is ______ (to one decimal place).

Answer and solution

Answer: $60.9$ (accepted range $\pm 0.1$ )

By superposition, $v_{o} = - \frac{R _{2}}{R _{1}} v_{1} + K v_{2}$ with $K = \frac{( R _{1} + R _{2} ) R _{4}}{R _{1} ( R _{3} + R _{4} )} = \frac{110 \times 101}{10 \times 111} = 10.009009$ .
Substituting $v_{1} = v_{c m} - v_{d} /2$ and $v_{2} = v_{c m} + v_{d} /2$ gives $A_{d} = \frac{1}{2} (10 + K) = 10.004505$ and $A_{c m} = K - 10 = 0.009009 = 1/111$ .
$CMRR = A_{d} / A_{c m} = 10.004505 \times 111 = 1110.5$ .
$20 lo g_{10} (1110.5) = 60.9$ dB. A 1% error in a single resistor limits the CMRR to about 61 dB even with a perfect op-amp.

PRACTICE 31 mark · MCQ

For which of the following circuits, built with an ideal op-amp and operating normally, is it NOT valid to assume $v_{+} = v_{-}$ ?

(A)
Voltage follower
(B)
Inverting integrator with a resistor $R_{f}$ across the capacitor
(C)
Inverting Schmitt trigger (output fed back to $v_{+}$ through a resistive divider, input applied at $v_{-}$ )
(D)
Three-op-amp instrumentation amplifier

Answer and solution

Answer: (C)

The virtual short needs net negative feedback with the output inside its linear range.
A, B and D feed the output back to the inverting input, so $v_{-} = v_{+}$ holds.
The Schmitt trigger feeds back to $v_{+}$ (positive feedback). Its output latches at $\pm V_{s a t}$ , and $v_{+} \neq = v_{-}$ except at the switching instant.

PRACTICE 41 mark · NAT

A three-op-amp instrumentation amplifier uses ideal op-amps. In the first stage, each op-amp has $R = 25 k Ω$ from its output to its inverting input, and $R_{G} = 1 k Ω$ joins the two inverting inputs. The difference stage is balanced, with input resistors $R_{3} = 10 k Ω$ and feedback and ground resistors $R_{4} = 20 k Ω$ . The inputs are $v_{1} = 2.000$ V and $v_{2} = 2.010$ V, and $v_{2}$ drives the op-amp whose output feeds the non-inverting side of the difference stage. The output voltage, in volts, is ______.

Answer and solution

Answer: $1.02$ (accepted range $\pm 0.005$ )

The virtual shorts put $v_{2} - v_{1} = 10$ mV across $R_{G}$ , so a current of $10 mV /1 k Ω = 10 μ$ A flows through $R$ , $R_{G}$ and $R$ in series.
$v_{o 2} = v_{2} + R (10 μ A) = 2.010 + 0.25 = 2.26$ V and $v_{o 1} = v_{1} - 0.25 = 1.75$ V, so $v_{o 2} - v_{o 1} = 0.51$ V $= (1 + 2 R / R_{G}) (10 mV) = 51 \times 10$ mV. The 2 V common-mode level appears at both outputs and cancels.
Difference stage: $v_{o} = \frac{R _{4}}{R _{3}} (v_{o 2} - v_{o 1}) = 2 \times 0.51 = 1.02$ V.

PRACTICE 52 marks · MSQ

A non-inverting amplifier has $R_{1} = 1 k Ω$ (from $v_{-}$ to ground) and $R_{f} = 99 k Ω$ . The op-amp is ideal except for an input offset voltage of magnitude 1 mV and input bias currents $I_{B 1} = 105$ nA into the inverting input and $I_{B 2} = 95$ nA into the non-inverting input. The signal source is an ideal voltage source (zero resistance) set to zero. Which of the following statements is/are correct?

(A)
The output error due to the offset voltage alone has magnitude 100 mV.
(B)
With the source connected directly to $v_{+}$ , the output error due to the bias currents alone is 10.395 mV.
(C)
Inserting a 990 Ω resistor in series with the non-inverting input reduces the output error due to the bias currents to 0.99 mV.
(D)
The 990 Ω resistor in option C also reduces the output error caused by the offset voltage.

Answer and solution

Answer: (A), (B), (C)

$V_{O S}$ is multiplied by the noise gain: $1 mV \times (1 + 99/1) = 100$ mV. A is correct.
With $v_{+} = 0$ , $v_{-} = 0$ , so no current flows in $R_{1}$ and all of $I_{B 1}$ flows through $R_{f}$ : $V_{o} = I_{B 1} R_{f} = 105 nA \times 99 k Ω = 10.395$ mV. B is correct.
$R_{1} ∥ R_{f} = \frac{1 \times 99}{100} k Ω = 990 Ω$ . With it, $v_{+} = - I_{B 2} (990 Ω)$ and $V_{o} = R_{f} (I_{B 1} - I_{B 2}) = 99 k Ω \times 10 nA = 0.99$ mV. C is correct.
The resistor balances only the bias currents. The offset-voltage term is still $V_{O S} (1 + R_{f} / R_{1}) = 100$ mV, so D is wrong.

PRACTICE 62 marks · NAT

An op-amp connected as a voltage follower ( $β = 1$ ) has loop gain $L (j f) = \frac{1 0 ^{5}}{( 1 + j f /10 ) ( 1 + j f / ( 2 \times 1 0 ^{6} ))}$ , with $f$ in Hz. Using the exact gain-crossover frequency (not the straight-line approximation), the phase margin, in degrees, is ______ (to one decimal place).

Answer and solution

Answer: $65.5$ (accepted range $\pm 0.2$ )

Well above 10 Hz, $∣ L ∣ \approx \frac{1 0 ^{5} \times 10}{f 1 + ( f / f _{2} ) ^{2}} = \frac{1 0 ^{6}}{f 1 + ( f / f _{2} ) ^{2}}$ with $f_{2} = 2$ MHz.
Let $x = f_{c} / f_{2}$ . Setting $∣ L ∣ = 1$ gives $\frac{1 0 ^{6}}{2 \times 1 0 ^{6} x 1 + x ^{2}} = 1$ , so $4 x^{4} + 4 x^{2} - 1 = 0$ and $x^{2} = \frac{2 - 1}{2} = 0.2071$ . Hence $x = 0.4551$ and $f_{c} = 910$ kHz.
Phase at crossover: $∠ L = - tan^{- 1} (f_{c} /10) - tan^{- 1} (0.4551) = - 89.99 9^{\circ} - 24.4 7^{\circ} = - 114.4 7^{\circ}$ .
$PM = 18 0^{\circ} - 114.4 7^{\circ} = 65. 5^{\circ}$ . The straight-line estimate (crossover at 1 MHz) would give $63. 4^{\circ}$ .
Cross-check: here $β f_{t} = 1$ MHz $= f_{2} /2$ , so $ζ = \frac{1}{2} 2 = 0.707$ , the maximally flat two-pole case, whose phase margin is $65. 5^{\circ}$ .

OFFICIAL GATE 2027 SYLLABUS WORDING

Copied from the GATE 2027 syllabus; see all 2027 syllabi.

GATE EC

Op-amp Circuits: Amplifiers, summers, differentiators, integrators … dominant-pole (Miller) compensation, phase margin

GATE EE

operational amplifiers: characteristics and applications

GATE IN

Characteristics of ideal and practical operational amplifiers; applications of opamps: adder, subtractor, integrator, differentiator, difference amplifier, instrumentation amplifier, precision rectifier

Preparing in Kolkata? IAE Academy's course for GATE ECE, GATE EE or GATE IN.