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GATE 2024 IN Q.59: solution and answer

GATE 2024 · INQ.59 · 2 marks · NAT

In the circuit shown, assume the opamp is ideal and the initial charge on the capacitor is zero. The output voltage at time t = 2 ms is ______ V (rounded off to one decimal place).

GATE 2024 IN question 59: Left: a plot of V_in against t.Tap to open full size
Figure from the GATE 2024 IN paper. It is part of the question.
Figure description

Left: a plot of V_in against t. V_in is a pulse train: 5 V from t = 0 to 1 ms, 0 V from 1 ms to 2 ms, 5 V again from 2 ms to 3 ms, then 0. Axis ticks are marked 1 ms, 2 ms, 3 ms, and the level is marked 5 V. Right: an inverting integrator. V_in goes through a 1 kΩ resistor to the inverting (−) input of the op-amp. A 2 µF capacitor connects the inverting input to the output V_out. The non-inverting (+) input is grounded. The op-amp is powered from supply rails V_CC and -V_EE, with no numerical values given.

Answer and solution

ANSWER

Official answer: -2.6 to -2.4Source: Official answer key, GATE 2024 IN (IISc Bengaluru)

  1. Assumptions: the op-amp is ideal (infinite gain, zero input current, output inside the supply rails, so not saturated) and the capacitor starts uncharged, so .

  2. Virtual short: the + input is grounded, so the − input sits at (virtual ground). The resistor current is therefore .

  3. KCL at the inverting node: no current enters the op-amp, so all of flows through the capacitor. The input side of is at 0 and the output side at , so , which gives

  4. Time constant: .

  5. For , is constant, so the output ramps down linearly:

  6. For , . No current flows through , so none flows through either. The capacitor keeps its charge and stays at .

  7. At the second pulse is only just starting. The integral is a continuous function of , so the step in has not added any area yet:

KEY IDEA

This is an inverting integrator. Its output equals minus the area under divided by , starting from the initial capacitor voltage. While there is no current, so the output holds its last value. Here the area up to 2 ms is and , so .

WATCH OUT FOR

(1) Treating the circuit as a passive RC charging exponentially with , e.g. . The virtual ground keeps the resistor current constant, so the output ramp is linear. (2) Assuming the output decays back to 0 during the 1–2 ms gap. With zero input there is no current, so the capacitor holds its charge. (3) Dropping the minus sign of the inverting integrator and answering . (4) Unit slips in (, not 2 s).

From the GATE 2024 IN paper. Every question of this paper · Download the full paper · All 36 Op-amps questions, with notes

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