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BJT and MOSFET biasing and DC analysis

Biasing sets a transistor's quiescent operating point (Q-point): the DC currents and voltages the signal swings about, and on which every small-signal parameter ( $g_{m}$ , $r_{π}$ , $r_{o}$ ) depends. A GATE biasing question usually asks you to do three things. First, decide the region of operation by assuming one and checking it. Second, solve the bias loop, which is one linear equation for a BJT (constant-drop model) and a quadratic for a MOSFET (square law), where you must keep the root that leaves the device on. Third, judge how well the Q-point holds against changes in $β$ , $V_{B E}$ , leakage and temperature, including the power the device dissipates.

13 previous-year questions · 13 solved · 6 practice questions

BJT regions, DC load line and Q-point

Conventions used in these notes. Transistors are npn unless stated. For a pnp, reverse every polarity and work with $V_{E B}$ , $V_{E C}$ and currents flowing out of the base and collector; all the npn equations then apply with positive numbers. The base-emitter junction uses the constant-drop model: $V_{B E} = 0.7$ V in the active region, and $V_{B E (s a t)} = 0.8$ V with $V_{C E (s a t)} = 0.2$ V in saturation. The Early effect is neglected ( $r_{o} \to \infty$ ). Collector leakage $I_{C O}$ (also written $I_{C B O}$ ) is neglected except when studying stability. Questions often give other values, such as 0.7 V for $V_{B E}$ in every region, or $V_{C E (s a t)} = 0.1$ V or 0.3 V. Always use the values the question gives.

A BJT has two junctions. Its region of operation depends on which of them is forward biased. DC analysis always follows the same pattern: assume a region, solve with that region's model, then check that the answer agrees with the assumption. Amplifiers are biased in the forward-active region. Switches use cut-off and saturation.

Region	B–E junction	B–C junction	Model used in DC analysis	Consistency check (npn)
Cut-off	Reverse (or below cut-in)	Reverse	$I_{B} = I_{C} = I_{E} = 0$	The base loop cannot supply $V_{B E} = 0.7$ V (solving gives $I_{B} \leq 0$ )
Forward active	Forward	Reverse	$V_{B E} = 0.7$ V, $I_{C} = β I_{B}$	$I_{B} > 0$ and $V_{C E} > V_{C E (s a t)}$
Saturation	Forward	Forward	$V_{B E} = 0.8$ V, $V_{C E} = 0.2$ V	$I_{B} > 0$ and $I_{C} < β I_{B}$ , i.e. $β_{forced} < β$
Reverse active	Reverse	Forward	Collector and emitter swap roles; current gain $β_{R} ≪ β$	Not a bias condition used for amplifiers

TERMINAL CURRENTS IN THE ACTIVE REGION

I_{C} = β I_{B}, I_{E} = I_{B} + I_{C} = (β + 1) I_{B}, α = \frac{β}{β + 1}, I_{C} = α I_{E}

Forward-active region only. With leakage included, $I_{C} = β I_{B} + (β + 1) I_{C O}$ . That is the form used to define the stability factor $S$ .

EXPONENTIAL MODEL OF THE ACTIVE REGION

I_{C} = I_{S} e^{V_{B E} / V_{T}}, V_{B E 2} - V_{B E 1} = V_{T} ln \frac{I _{C 2}}{I _{C 1}}

Forward active with $V_{B E} ≫ V_{T}$ and the Early effect neglected. $I_{S}$ is the saturation current, proportional to the emitter area, and $V_{T}$ is the thermal voltage (25 mV or 26 mV at room temperature; use the question's value). The constant-drop model replaces this curve by a fixed $V_{B E}$ . Each decade of collector current changes $V_{B E}$ by $V_{T} ln 10$ : about 58 mV with $V_{T} = 25$ mV, or 60 mV with $V_{T} = 26$ mV. If an Early voltage $V_{A}$ is given, multiply $I_{C}$ by $(1 + V_{C E} / V_{A})$ ; the output resistance is then $r_{o} = V_{A} / I_{C}$ .

Finding the region of a BJT (npn)

Assume forward active. Put $V_{B E} = 0.7$ V and write KVL round the base loop to find $I_{B}$ (the master equation in the next section does this for every standard circuit).
If this gives $I_{B} \leq 0$ , the junction cannot turn on. The transistor is cut off: $I_{B} = I_{C} = 0$ , and each node voltage follows from its resistors carrying zero current.
Otherwise take $I_{C} = β I_{B}$ and $I_{E} = (β + 1) I_{B}$ , and find $V_{C E}$ from the collector loop.
If $V_{C E} > V_{C E (s a t)}$ , the assumption holds. The transistor is active and you have the Q-point.
If $V_{C E} \leq V_{C E (s a t)}$ , or $V_{C E}$ comes out negative, the transistor is saturated. Put $V_{B E} = V_{B E (s a t)}$ and $V_{C E} = V_{C E (s a t)}$ , solve the base and collector loops (together if they share an emitter resistor), and confirm that $I_{B} > 0$ and $I_{C} < β I_{B}$ .

DC LOAD LINE

V_{C E} = V_{C C} - I_{C} R_{C} - I_{E} R_{E} \approx V_{C C} - I_{C} (R_{C} + R_{E})

KVL round the collector loop, drawn on the $I_{C}$ – $V_{C E}$ output characteristics, for circuits in which $R_{C}$ carries $I_{C}$ (in collector-feedback bias it carries $I_{E}$ ; see the next section). The intercepts are $V_{C E} = V_{C C}$ at $I_{C} = 0$ (the cut-off end) and $I_{C} = V_{C C} / (R_{C} + R_{E})$ at $V_{C E} = 0$ . The approximate form takes $I_{E} \approx I_{C}$ (large $β$ ).

COLLECTOR CURRENT AT SATURATION

I_{C (s a t)} = \frac{V _{C C} - V _{C E (s a t)}}{R _{C} + R _{E}}

The largest collector current the external circuit allows, however hard the base is driven. With $R_{E} = 0$ it is exact: $(V_{C C} - V_{C E (s a t)}) / R_{C}$ . With $R_{E}$ present it assumes $I_{E} \approx I_{C}$ , which can be poor in saturation because the base current is no longer small compared with $I_{C}$ and also flows in $R_{E}$ ; for an exact answer solve the base and collector loops together.

The Q-point $(V_{C E Q}, I_{C Q})$ is where the load line crosses the output characteristic for the actual base current. The output can swing along the load line from $V_{C E (s a t)}$ up to $V_{C C}$ . A Q-point close to saturation clips the half-cycle that drives $V_{C E}$ down. A Q-point close to cut-off clips the half-cycle that drives $I_{C}$ towards zero. When the signal sees the same load as the DC circuit, the largest symmetrical swing comes from a Q-point at the middle of the load line, $V_{C E Q} = (V_{C C} + V_{C E (s a t)}) /2 \approx V_{C C} /2$ .

Q-POINT FOR MAXIMUM SYMMETRICAL SWING (AC LOAD LINE)

I_{C Q} = \frac{V _{C C}}{R _{d c} + R _{a c}}, V_{C E Q} = I_{C Q} R_{a c}

Use this when the signal-frequency load differs from the DC load. $R_{d c} = R_{C} + R_{E}$ is the DC collector-loop resistance. $R_{a c}$ is what the collector sees at signal frequencies, e.g. $R_{C} ∥ R_{L}$ with $R_{E}$ bypassed. It places the Q-point at the middle of the AC load line, and neglects $V_{C E (s a t)}$ and leakage and takes $I_{E} \approx I_{C}$ . With $R_{a c} = R_{d c}$ it reduces to the midpoint, $V_{C E Q} = V_{C C} /2$ .

EXAM TIP

A computed $V_{C E}$ that is positive but below $V_{C E (s a t)}$ (say 0.1 V) still means saturation. The test is $V_{C E} > V_{C E (s a t)}$ , not $V_{C E} > 0$ . Once the check fails, drop $I_{C} = β I_{B}$ : in saturation the collector current is set by the collector circuit alone.

BJT bias circuits

Every standard BJT bias circuit reduces (after a Thévenin step where needed) to one base loop: a source $V_{B B}$ , a resistance $R_{B B}$ in series with the base, the B–E drop, and a resistance $R_{x}$ that carries the emitter current $(β + 1) I_{B}$ . KVL round that loop gives one master equation. The circuits differ only in what $V_{B B}$ , $R_{B B}$ and $R_{x}$ are. A resistance carrying the emitter current appears in the base loop multiplied by $(β + 1)$ . This 'reflection' is also why an emitter resistor stabilises the Q-point.

MASTER BASE-LOOP EQUATION (ACTIVE REGION)

I_{B} = \frac{V _{B B} - V _{B E}}{R _{B B} + ( β + 1 ) R _{x}}, I_{C} = \frac{β ( V _{B B} - V _{B E} )}{R _{B B} + ( β + 1 ) R _{x}}

npn, forward active, leakage neglected. Read $V_{B B}$ , $R_{B B}$ and $R_{x}$ for each circuit from the table below, then find $V_{C E}$ from the collector loop and check that it exceeds $V_{C E (s a t)}$ .

Circuit	$V_{B B}$	$R_{B B}$	$R_{x}$	$V_{C E}$
Fixed bias ( $R_{B}$ from $V_{C C}$ to base, emitter grounded)	$V_{C C}$	$R_{B}$	$0$	$V_{C C} - I_{C} R_{C}$
Emitter bias ( $R_{B}$ from $V_{C C}$ , $R_{E}$ in emitter)	$V_{C C}$	$R_{B}$	$R_{E}$	$V_{C C} - I_{C} R_{C} - I_{E} R_{E}$
Collector-to-base (collector feedback), $R_{B}$ from collector to base	$V_{C C}$	$R_{B}$	$R_{C} + R_{E}$	$V_{C C} - I_{E} (R_{C} + R_{E})$
Voltage divider ( $R_{1}$ from $V_{C C}$ to base, $R_{2}$ base to ground)	$\frac{V _{C C} R _{2}}{R _{1} + R _{2}}$	$R_{1} ∥ R_{2}$	$R_{E}$	$V_{C C} - I_{C} R_{C} - I_{E} R_{E}$
Two-supply emitter bias (base to ground via $R_{B}$ , $R_{E}$ to $- V_{E E}$ )	$V_{E E}$	$R_{B}$	$R_{E}$	$V_{C C} + V_{E E} - I_{C} R_{C} - I_{E} R_{E}$

FIXED BIAS

I_{B} = \frac{V _{C C} - V _{B E}}{R _{B}}, I_{C} = β I_{B}, V_{C E} = V_{C C} - I_{C} R_{C}

$I_{B}$ is fixed by $R_{B}$ alone, so $I_{C}$ is directly proportional to $β$ . Changing the transistor, or its temperature, changes $I_{C Q}$ by the same fraction as $β$ changes.

COLLECTOR-TO-BASE (COLLECTOR-FEEDBACK) BIAS

I_{B} = \frac{V _{C C} - V _{B E}}{R _{B} + ( β + 1 ) ( R _{C} + R _{E} )}, V_{C E} = V_{C C} - I_{E} (R_{C} + R_{E})

$R_{B}$ runs from collector to base. $R_{C}$ carries $I_{C} + I_{B} = I_{E}$ , not $I_{C}$ . Put $R_{E} = 0$ if there is no emitter resistor. If $I_{C}$ tries to rise, $V_{C}$ falls and so does $I_{B}$ : that is the negative feedback.

VOLTAGE-DIVIDER BIAS: EXACT (THÉVENIN) ANALYSIS

V_{B B} = \frac{V _{C C} R _{2}}{R _{1} + R _{2}}, R_{B B} = R_{1} ∥ R_{2} = \frac{R _{1} R _{2}}{R _{1} + R _{2}}, I_{B} = \frac{V _{B B} - V _{B E}}{R _{B B} + ( β + 1 ) R _{E}}

Exact within the constant-drop model. Use it whenever $β$ is given and the approximate condition below is not clearly met, or when the question asks how $I_{C}$ changes with $β$ .

VOLTAGE-DIVIDER BIAS: APPROXIMATE ANALYSIS

V_{B} \approx V_{B B} = \frac{V _{C C} R _{2}}{R _{1} + R _{2}}, I_{C} \approx I_{E} = \frac{V _{B B} - V _{B E}}{R _{E}}, valid if β R_{E} \geq 10 R_{2}

Ignores the base current's loading of the divider. Under the stated condition, $R_{B B} / ((β + 1) R_{E}) < 0.1$ , so $I_{E}$ is overestimated by less than 10% (and $I_{C}$ by a further factor $(β + 1) / β$ ). The larger $β R_{E} / R_{2}$ , the smaller the error. The result does not depend on $β$ , which is why this circuit gives a Q-point that is nearly independent of the transistor's $β$ .

TWO-SUPPLY EMITTER BIAS

I_{E} = \frac{V _{E E} - V _{B E}}{R _{E} + R _{B} / ( β + 1 )} \approx \frac{V _{E E} - V _{B E}}{R _{E}}

Base returned to ground through $R_{B}$ , emitter to $- V_{E E}$ through $R_{E}$ . The approximation holds when $R_{B} / (β + 1) ≪ R_{E}$ . The emitter sits at $V_{E} = - V_{B E} - I_{B} R_{B}$ , which is about $- V_{B E}$ when the drop $I_{B} R_{B}$ is small (exactly $- V_{B E}$ with the base grounded directly).

WORKED EXAMPLE

An npn transistor with $β = 100$ and $V_{B E} = 0.7$ V is biased from $V_{C C} = 12$ V by a divider: $R_{1} = 40$ kΩ from $V_{C C}$ to base and $R_{2} = 10$ kΩ from base to ground. $R_{C} = 4$ kΩ and $R_{E} = 1$ kΩ. Find the Q-point exactly and compare it with the approximate method. Then find the stability factor $S$ and the power dissipated in the transistor.

Solution

Thévenin equivalent of the divider: $V_{B B} = 12 \times 10/50 = 2.4$ V and $R_{B B} = 40 ∥ 10 = 8$ kΩ.
Assume active: $I_{B} = \frac{2.4 - 0.7}{8 + 101 \times 1} mA = \frac{1.7}{109} mA = 15.60 μ A$ .
$I_{C} = 100 I_{B} = 1.560$ mA and $I_{E} = 101 I_{B} = 1.575$ mA.
$V_{C E} = 12 - 1.560 \times 4 - 1.575 \times 1 = 4.19$ V. This is above 0.2 V, so the transistor is active and the assumption holds.
Approximate method: $β R_{E} = 100$ kΩ and $10 R_{2} = 100$ kΩ, so the condition is only just met. $I_{C} \approx I_{E} \approx (2.4 - 0.7) /1 k = 1.7$ mA and $V_{C E} \approx 12 - 1.7 \times 5 = 3.5$ V. At the limit of the condition, the collector current comes out about 9% high.
Stability: $S = \frac{( 1 + β ) ( R _{B B} + R _{E} )}{R _{B B} + ( 1 + β ) R _{E}} = \frac{101 \times 9}{8 + 101} = 8.34$ . Fixed bias with the same $β$ would give $S = 101$ .
Power: $P_{D} = V_{C E} I_{C} + V_{B E} I_{B} = 4.186 \times 1.560 + 0.7 \times 0.0156 \approx 6.53 + 0.01 = 6.54$ mW.

Answer: $I_{C Q} = 1.56$ mA and $V_{C E Q} = 4.19$ V (the approximate method gives 1.7 mA and 3.5 V). $S \approx 8.34$ and $P_{D} \approx 6.54$ mW.

EXAM TIP

The approximate divider result does not contain $β$ . If a question asks how much $I_{C}$ changes when $β$ changes (say from 100 to 200), the approximate method would answer 'zero'. Use the exact Thévenin form instead.

EXAM TIP

A collector-to-base biased transistor (no other resistor at the base) cannot saturate while it conducts. With the base fed from the collector, $V_{C B} = I_{B} R_{B} \geq 0$ , so the collector junction is never forward biased, and $V_{C E} = V_{B E} + I_{B} R_{B} \geq V_{B E}$ always exceeds $V_{C E (s a t)}$ . You can skip the saturation check for this circuit.

Stability factors S, S′ and S″

The collector current drifts with temperature through three parameters. The leakage $I_{C O}$ roughly doubles for every 10 °C rise (a common rule of thumb). $V_{B E}$ at constant current falls by roughly 2 to 2.5 mV/°C. $β$ rises with temperature and also varies widely between transistors of the same type. A stability factor is the sensitivity of $I_{C}$ to one of these parameters with the other two held constant. The smaller its magnitude, the more stable the Q-point. For $S$ , the ideal lower limit is 1.

DEFINITIONS OF THE STABILITY FACTORS

S = \frac{\partial I _{C}}{\partial I _{C O}}, S^{'} = \frac{\partial I _{C}}{\partial V _{B E}}, S^{''} = \frac{\partial I _{C}}{\partial β}

Each partial derivative holds the other two parameters constant. $S$ has no units, $S^{'}$ is in A/V and negative ( $I_{C}$ falls as $V_{B E}$ rises), and $S^{''}$ is in A.

TOTAL DRIFT OF THE COLLECTOR CURRENT

Δ I_{C} \approx S Δ I_{C O} + S^{'} Δ V_{B E} + S^{''} Δ β

First-order, for small changes. When temperature rises, $Δ V_{B E} < 0$ and $S^{'} < 0$ , so the $V_{B E}$ term also increases $I_{C}$ . All three terms push $I_{C}$ the same way.

GENERAL EXPRESSION FOR S

S = \frac{1 + β}{1 - β \frac{\partial I _{B}}{\partial I _{C}}}

Obtained by differentiating $I_{C} = β I_{B} + (1 + β) I_{C O}$ with respect to $I_{C}$ at constant $β$ . Get $\partial I_{B} / \partial I_{C}$ from the circuit's base-loop KVL. It is zero for fixed bias and negative whenever the circuit has feedback, which is what pulls $S$ below $1 + β$ .

S FOR ANY CIRCUIT OF THE MASTER FORM

S = \frac{( 1 + β ) ( R _{B B} + R _{x} )}{R _{B B} + ( 1 + β ) R _{x}} = \frac{1 + β}{1 + \frac{β R _{x}}{R _{B B} + R _{x}}}

$R_{B B}$ and $R_{x}$ come from the bias-circuit table. $S$ runs from $1 + β$ for fixed bias ( $R_{x} = 0$ ) down to about $1 + R_{B B} / R_{x}$ when $(1 + β) R_{x} ≫ R_{B B}$ . A small $R_{B B} / R_{E}$ ratio therefore means good stability.

S′ (SENSITIVITY TO V_BE)

S^{'} = \frac{- β}{R _{B B} + ( 1 + β ) R _{x}}

Master form. Fixed bias: $S^{'} = - β / R_{B}$ . Divider or emitter bias: $S^{'} \approx - 1/ R_{E}$ when $(1 + β) R_{E} ≫ R_{B B}$ and $β ≫ 1$ .

S″ (SENSITIVITY TO Β), SMALL CHANGE

S^{''} = \frac{I _{C} S}{β ( 1 + β )}

Master form, leakage neglected. For fixed bias ( $S = 1 + β$ ), $S^{''} = I_{C} / β = I_{B}$ , the largest possible for a given $I_{C}$ and $β$ .

S″ FOR A LARGE CHANGE OF Β

S^{''} = \frac{Δ I _{C}}{Δ β} = \frac{I _{C 1} S _{2}}{β _{1} ( 1 + β _{2} )}

Exact within the master form (leakage neglected) when $β$ changes from $β_{1}$ to $β_{2}$ . $I_{C 1}$ is the collector current at $β_{1}$ , and $S_{2}$ is $S$ evaluated with $β_{2}$ . Then $Δ I_{C} = S^{''} (β_{2} - β_{1})$ .

Circuit	$S$	$S^{'}$
Fixed bias	$1 + β$	$- β / R_{B}$
Emitter bias ( $R_{B}$ , $R_{E}$ )	$\frac{( 1 + β ) ( R _{B} + R _{E} )}{R _{B} + ( 1 + β ) R _{E}}$	$\frac{- β}{R _{B} + ( 1 + β ) R _{E}}$
Collector-to-base ( $R_{E} = 0$ )	$\frac{1 + β}{1 + β R _{C} / ( R _{B} + R _{C} )}$	$\frac{- β}{R _{B} + ( 1 + β ) R _{C}}$
Voltage divider	$\frac{( 1 + β ) ( R _{B B} + R _{E} )}{R _{B B} + ( 1 + β ) R _{E}}$ , which is $\approx 1 + \frac{R _{B B}}{R _{E}}$ if $(1 + β) R_{E} ≫ R_{B B}$	$\frac{- β}{R _{B B} + ( 1 + β ) R _{E}}$

EXAM TIP

In collector-to-base bias ( $R_{E} = 0$ ), $R_{C}$ plays the part of $R_{x}$ , but $R_{B} / R_{C}$ cannot be chosen freely. KVL gives $R_{B} / ((β + 1) R_{C}) = (V_{C E Q} - V_{B E}) / (V_{C C} - V_{C E Q})$ , so once the Q-point is chosen that ratio, and with it $S$ , is fixed. For $V_{C E Q} = (V_{C C} + V_{B E}) /2$ the ratio is 1, $R_{B} = (β + 1) R_{C}$ and $S = (β + 2) /2$ , about half the fixed-bias value. In divider bias, $R_{B B} / R_{E}$ can be made small without moving the Q-point (at the cost of more divider current), so $S$ can be brought much lower: 8.34 in the worked example above.

EXAM TIP

Compare stability factors of different circuits at the same $β$ . The negative feedback that lowers $S$ (an emitter resistor or collector feedback) also lowers the signal gain unless it is removed at signal frequencies, e.g. by bypassing $R_{E}$ with a capacitor. Bypassing does not change the DC stability.

BJT as a switch

As a switch, the transistor is driven between two states. OFF is cut-off: $I_{C} \approx 0$ and $V_{C E} \approx V_{C C}$ . ON is saturation: $V_{C E} = V_{C E (s a t)}$ and $I_{C}$ is set by the load. The active region is only passed through during switching. The design question is always the same: is the base drive large enough to guarantee saturation?

CONDITION FOR SATURATION

I_{B} > I_{B (E O S)} = \frac{I _{C (s a t)}}{β}, I_{C (s a t)} = \frac{V _{C C} - V _{C E (s a t)}}{R _{C}}

$I_{B (E O S)}$ is the base current at the edge of saturation. Emitter grounded; with an emitter resistor, use $R_{C} + R_{E}$ and solve both loops together. To guarantee saturation for every device of a type, use $β_{min}$ .

FORCED BETA AND OVERDRIVE FACTOR

β_{forced} = \frac{I _{C (s a t)}}{I _{B}} < β, ODF = \frac{I _{B}}{I _{B (E O S)}} = \frac{β}{β _{forced}}

In saturation, the ratio $I_{C} / I_{B}$ is set by the external circuit, not by the transistor. The transistor is saturated when $β_{forced} < β$ (ODF > 1). Designs deliberately keep $β_{forced}$ well below $β$ for a margin.

MINIMUM INPUT VOLTAGE FOR SATURATION

V_{in (min)} = V_{B E (s a t)} + \frac{I _{C (s a t)}}{β} R_{B}

Base driven from $V_{in}$ through $R_{B}$ , emitter grounded. At this input the transistor is at the edge of saturation. Some solutions use 0.7 V in place of $V_{B E (s a t)}$ ; follow the question.

EXAM TIP

Quick test for fixed bias with $R_{B}$ returned to the same $V_{C C}$ : the transistor saturates when $β (V_{C C} - V_{B E}) / R_{B} > (V_{C C} - V_{C E (s a t)}) / R_{C}$ . That is, when $β R_{C} > R_{B} (V_{C C} - V_{C E (s a t)}) / (V_{C C} - V_{B E})$ , roughly when $β R_{C}$ exceeds $R_{B}$ . A larger $R_{C}$ , a larger $β$ or a smaller $R_{B}$ all push the transistor towards saturation.

EXAM TIP

With the emitter grounded, the base and collector loops of a saturated transistor are independent. Find $I_{B}$ from the base loop with $V_{B E (s a t)}$ , and $I_{C}$ from the collector loop with $V_{C E (s a t)}$ . The static dissipation is small in either state: about zero when OFF, and $V_{C E (s a t)} I_{C} + V_{B E (s a t)} I_{B}$ when ON. The dissipation during the transitions is not included in these figures.

MOSFET regions of operation

Conventions. Enhancement NMOS unless stated, with the long-channel square law and $k_{n} = μ_{n} C_{o x} (W / L)$ in A/V². The threshold voltage is written $V_{T H}$ to keep $V_{T}$ free for the thermal voltage. Overdrive is $V_{O V} = V_{GS} - V_{T H}$ . Channel-length modulation is neglected ( $λ = 0$ ) unless a value is given. The source is tied to the body (no body effect) unless stated. The gate draws no DC current ( $I_{G} = 0$ ), so a gate bias network is never loaded by the transistor. Cut-off: for $V_{GS} < V_{T H}$ there is no channel and $I_{D} = 0$ (subthreshold current neglected).

TRIODE (LINEAR, OHMIC) REGION

I_{D} = k_{n} [(V_{GS} - V_{T H}) V_{D S} - \frac{V _{D S}^{2}}{2}], V_{GS} \geq V_{T H}, 0 \leq V_{D S} \leq V_{GS} - V_{T H}

The channel exists all the way from source to drain. The current depends on both $V_{GS}$ and $V_{D S}$ .

SATURATION REGION

I_{D} = \frac{1}{2} k_{n} (V_{GS} - V_{T H})^{2} (1 + λ V_{D S}), V_{GS} \geq V_{T H}, V_{D S} \geq V_{GS} - V_{T H}

The channel is pinched off at the drain end. With $λ = 0$ , $I_{D}$ does not depend on $V_{D S}$ , and the triode and saturation equations agree at the boundary $V_{D S} = V_{O V}$ , where $I_{D} = \frac{1}{2} k_{n} V_{D S}^{2}$ . When $λ$ is given, the small-signal output resistance is $r_{o} \approx 1/ (λ I_{D})$ .

SATURATION TEST FROM TERMINAL VOLTAGES

saturation ⟺ V_{G D} \leq V_{T H} ⟺ V_{D} \geq V_{G} - V_{T H}

Equivalent to $V_{D S} \geq V_{O V}$ (NMOS, device on). Handy when node voltages are known: the drain may sit at most $V_{T H}$ below the gate. If $V_{G D} > V_{T H}$ , a channel exists at the drain end as well and the device is in triode.

DEEP-TRIODE ON RESISTANCE

r_{D S} = \frac{1}{k _{n} ( V _{GS} - V _{T H} )}, V_{D S} ≪ 2 (V_{GS} - V_{T H})

The $V_{D S}^{2}$ term is negligible here, so the MOSFET behaves as a resistor controlled by $V_{GS}$ . This is the ON resistance of a MOSFET switch.

DEPLETION NMOS

I_{D S S} = \frac{1}{2} k_{n} V_{T H}^{2}, I_{D} = I_{D S S} (1 - \frac{V _{GS}}{V _{T H}})^{2} (saturation)

For a depletion NMOS, $V_{T H} < 0$ (often written $V_{P}$ ). A channel already exists at $V_{GS} = 0$ , and $I_{D S S}$ is the saturation current there. The same triode and saturation equations and tests apply. $V_{GS}$ may be negative (depletion mode) or positive (enhancement mode).

ENHANCEMENT PMOS

I_{S D} = \frac{1}{2} k_{p} (V_{S G} - ∣ V_{T P} ∣)^{2}, on if V_{S G} \geq ∣ V_{T P} ∣, saturated if V_{S D} \geq V_{S G} - ∣ V_{T P} ∣

Here $V_{T P} < 0$ and $k_{p} = μ_{p} C_{o x} (W / L)$ . Current flows from source to drain. In triode ( $V_{S D} < V_{S G} - ∣ V_{T P} ∣$ ), $I_{S D} = k_{p} [(V_{S G} - ∣ V_{T P} ∣) V_{S D} - V_{S D}^{2} /2]$ . Working with $V_{S G}$ , $V_{S D}$ and $∣ V_{T P} ∣$ keeps every quantity positive, and the NMOS rules carry over unchanged.

BODY EFFECT

V_{T H} = V_{T H 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F})

NMOS whose source is above its body ( $V_{S B} \geq 0$ ). $V_{T H 0}$ is the threshold at $V_{S B} = 0$ , $γ$ is the body-effect coefficient (in V $^{1/2}$ ) and $ϕ_{F}$ is the substrate's Fermi potential; use the symbols the question gives. The threshold rises as $V_{S B}$ rises, which lowers $I_{D}$ at a given $V_{GS}$ .

Device	Threshold	Conducts when	Saturated when
Enhancement NMOS	$V_{T H} > 0$	$V_{GS} > V_{T H}$	$V_{D S} \geq V_{GS} - V_{T H}$
Depletion NMOS	$V_{T H} < 0$	$V_{GS} > V_{T H}$ (on at $V_{GS} = 0$ )	$V_{D S} \geq V_{GS} - V_{T H}$
Enhancement PMOS	$V_{T P} < 0$	$V_{S G} > ∣ V_{T P} ∣$	$V_{S D} \geq V_{S G} - ∣ V_{T P} ∣$
Depletion PMOS	$V_{T P} > 0$	$V_{GS} < V_{T P}$ (on at $V_{GS} = 0$ )	$V_{S D} \geq V_{S G} + V_{T P}$

EXAM TIP

Check how the question defines its parameter. $k_{n}^{'} = μ_{n} C_{o x}$ is the process parameter and $k_{n} = k_{n}^{'} (W / L)$ the device parameter. Some write $I_{D} = K (V_{GS} - V_{T H})^{2}$ with $K = k_{n} /2$ . Putting $K$ in where $k_{n}$ is meant, or the reverse, gives a factor-of-2 error in $I_{D}$ .

EXAM TIP

The region test uses only voltages. $k_{n}$ and $W / L$ scale the current but never decide the region by themselves when $V_{GS}$ and $V_{D S}$ are known. In the symmetric device the square law describes, source and drain are interchangeable: in an NMOS the drain is whichever of the two terminals is at the higher potential, so relabel if the circuit puts the labelled 'drain' lower.

MOSFET biasing and diode-connected transistors

Because $I_{G} = 0$ , the gate voltage comes straight from the gate network. A divider gives $V_{G} = V_{D D} R_{2} / (R_{1} + R_{2})$ exactly, with no loading correction. Every standard arrangement then gives one bias line, $V_{GS} = V_{X} - I_{D} R_{X}$ , and combining it with the saturation equation gives a quadratic. A source resistor stabilises the Q-point. If $I_{D}$ tries to rise (a lower $V_{T H}$ or a higher $k_{n}$ ), $V_{S}$ rises, $V_{GS}$ falls and the rise is opposed. Fixed bias has no such feedback. There $I_{D} \propto (V_{G} - V_{T H})^{2}$ follows every spread in $V_{T H}$ and $k_{n}$ directly.

Circuit	$V_{X}$	$R_{X}$	Remarks
Fixed bias (gate divider, source grounded)	$V_{G}$	$0$	$V_{GS} = V_{G}$ ; no feedback
Voltage divider with source resistor	$V_{G} = \frac{V _{D D} R _{2}}{R _{1} + R _{2}}$	$R_{S}$	The standard stable bias
Self bias (gate to ground through $R_{G}$ )	$0$	$R_{S}$	Works only for depletion devices; an enhancement NMOS stays off
Drain feedback ( $R_{G}$ from drain to gate, source grounded)	$V_{D D}$	$R_{D}$	$V_{GS} = V_{D S}$ , so always saturated when on
Two supplies (gate grounded, $R_{S}$ to $- V_{S S}$ )	$V_{S S}$	$R_{S}$	$V_{GS} = V_{S S} - I_{D} R_{S}$

BIAS LINE AND THE ROOT THAT KEEPS THE DEVICE ON

V_{GS} = V_{X} - I_{D} R_{X}, V_{O V} = \frac{- 1 + 1 + 2 k _{n} R _{X} ( V _{X} - V _{T H} )}{k _{n} R _{X}}, I_{D} = \frac{1}{2} k_{n} V_{O V}^{2}

This is the positive root of $\frac{1}{2} k_{n} R_{X} V_{O V}^{2} + V_{O V} - (V_{X} - V_{T H}) = 0$ , assuming saturation, $λ = 0$ and $R_{X} > 0$ . It needs $V_{X} > V_{T H}$ ; otherwise the device is off. Afterwards, check $V_{D S} \geq V_{O V}$ . With $R_{X} = 0$ , simply $V_{O V} = V_{X} - V_{T H}$ .

DC analysis of a MOSFET bias circuit

Find $V_{G}$ from the gate network, using $I_{G} = 0$ .
Assume saturation and write $I_{D} = \frac{1}{2} k_{n} (V_{X} - I_{D} R_{X} - V_{T H})^{2}$ .
Solve the quadratic and keep the root with $V_{GS} > V_{T H}$ ( $V_{O V} > 0$ ). It is always the smaller $I_{D}$ . The larger root gives $V_{GS} < V_{T H}$ , which describes a device that would be off, where the square law does not apply.
Find $V_{S}$ and $V_{D}$ , then check $V_{D S} \geq V_{O V}$ (equivalently $V_{G D} \leq V_{T H}$ ).
If the check fails, the device is in triode. Redo step 2 with the triode equation on the same bias line, and keep the root with $V_{GS} > V_{T H}$ and $V_{D S} < V_{O V}$ .

WORKED EXAMPLE

An enhancement NMOS has $V_{T H} = 1$ V, $k_{n} = μ_{n} C_{o x} (W / L) = 2$ mA/V² and $λ = 0$ . It is biased from $V_{D D} = 14$ V by a gate divider $R_{1} = R_{2} = 1$ MΩ, with $R_{D} = 1.5$ kΩ and $R_{S} = 1$ kΩ. Find $I_{D}$ , $V_{D S}$ , the region, and the power dissipated in the transistor.

Solution

$V_{G} = 14 \times 1/ (1 + 1) = 7$ V. There is no gate current, so the divider is unloaded.
Assume saturation. With $I_{D}$ in mA and $R_{S} = 1$ kΩ, $V_{GS} = 7 - I_{D}$ and $I_{D} = \frac{1}{2} (2) (V_{GS} - 1)^{2} = (6 - I_{D})^{2}$ .
$I_{D}^{2} - 13 I_{D} + 36 = 0$ , so $(I_{D} - 4) (I_{D} - 9) = 0$ and $I_{D} = 4$ mA or 9 mA.
$I_{D} = 9$ mA gives $V_{GS} = 7 - 9 = - 2$ V, which is below $V_{T H}$ , so the device would be off. Reject it. $I_{D} = 4$ mA gives $V_{GS} = 3$ V and $V_{O V} = 2$ V. As a cross-check, the closed form with $k_{n} R_{X} = 2 \times 1 = 2$ V $^{- 1}$ gives $V_{O V} = (- 1 + 1 + 2 \times 2 \times 6) /2 = (- 1 + 5) /2 = 2$ V.
$V_{S} = 4 \times 1 = 4$ V and $V_{D} = 14 - 4 \times 1.5 = 8$ V, so $V_{D S} = 4$ V. This is at least $V_{O V} = 2$ V, so saturation is confirmed.
$P_{D} = V_{D S} I_{D} = 4 \times 4 = 16$ mW.

Answer: $I_{D} = 4$ mA, $V_{D S} = 4$ V, saturation, $P_{D} = 16$ mW.

Diode-connected transistors. Tying the gate of a MOSFET to its drain, or the base of a BJT to its collector, turns the device into a two-terminal element. It carries whatever current is forced through it and develops the matching $V_{GS}$ or $V_{B E}$ . Such devices are used as bias references (the input side of a current mirror), level shifters and active loads.

DIODE-CONNECTED MOSFET

V_{D S} = V_{GS} \Rightarrow saturation whenever V_{GS} > V_{T H}, V_{GS} = V_{T H} + \frac{2 I _{D}}{k _{n}}

Gate tied to drain (enhancement device, $λ = 0$ ). Since $V_{D S} = V_{GS} > V_{GS} - V_{T H}$ , it can never enter triode. Its small-signal resistance is $1/ g_{m}$ (in parallel with $r_{o}$ if one is given; body effect neglected), where $g_{m} = k_{n} V_{O V} = 2 k_{n} I_{D} = 2 I_{D} / V_{O V}$ .

DIODE-CONNECTED BJT

V_{C B} = 0 \Rightarrow active region, I = I_{C} + I_{B} = I_{C} (1 + \frac{1}{β}), r \approx \frac{1}{g _{m}} = \frac{V _{T}}{I _{C}}

Base tied to collector. The collector junction has zero bias, so it is not forward biased and $I_{C} = β I_{B}$ still holds. The small-signal resistance is $r_{π} ∥ (1/ g_{m}) \approx 1/ g_{m}$ (hybrid- $π$ model with $g_{m} = I_{C} / V_{T}$ and $r_{π} = β / g_{m}$ ), with thermal voltage $V_{T} \approx 25$ mV at room temperature (use 26 mV if the question does).

CURRENT MIRROR BUILT ON A DIODE-CONNECTED DEVICE

I_{o u t} = I_{r e f} \frac{( W / L ) _{2}}{( W / L ) _{1}} (MOSFET), I_{o u t} = \frac{I _{r e f}}{1 + 2/ β} (matched BJTs)

The diode-connected device sets $V_{GS}$ (or $V_{B E}$ ) for a second device. The MOSFETs share $V_{T H}$ and $μ_{n} C_{o x}$ and differ only in $W / L$ ; the BJTs are identical (same $I_{S}$ and $β$ ), so $I_{r e f} = I_{C} + 2 I_{B}$ . Valid while the output device stays saturated (MOSFET) or active (BJT), with $λ = 0$ and the Early effect neglected.

EXAM TIP

Drain-feedback bias behaves like a diode connection at DC. With $I_{G} = 0$ there is no drop across $R_{G}$ , so $V_{G} = V_{D}$ , and an enhancement NMOS in this circuit is saturated whenever it conducts. No region check is needed.

EXAM TIP

Self bias ( $V_{G} = 0$ , resistor in the source) cannot turn on an enhancement NMOS, because $V_{GS} = - I_{D} R_{S} \leq 0 < V_{T H}$ . If a question shows this circuit with an enhancement device, the device is off and $I_{D} = 0$ . For a depletion device the same bias line gives a valid Q-point: keep the root with $V_{T H} < V_{GS} \leq 0$ , i.e. $I_{D} \leq I_{D S S}$ .

Power dissipation, junction temperature and thermal runaway

DC POWER DISSIPATED IN THE DEVICE

P_{D} = V_{C E} I_{C} + V_{B E} I_{B} \approx V_{C E} I_{C} (BJT), P_{D} = V_{D S} I_{D} (MOSFET)

Quiescent power turned into heat in the transistor. The base term is usually negligible. A MOSFET has no gate term because $I_{G} = 0$ .

POWER DRAWN FROM THE SUPPLY

P_{C C} = V_{C C} \times (total DC current drawn from V_{C C})

This includes the bias-divider current as well as the collector (drain) current. The supply power equals the power in all the resistors plus the power in the transistor.

MAXIMUM DEVICE DISSIPATION ON A RESISTIVE LOAD LINE

P_{D, ma x} = \frac{V _{C C}^{2}}{4 R} at V_{C E} = \frac{V _{C C}}{2}, I_{C} = \frac{V _{C C}}{2 R}

$R = R_{C} + R_{E}$ for a BJT (DC load line, $I_{E} \approx I_{C}$ ). For a MOSFET, replace $V_{C C}$ by $V_{D D}$ , $V_{C E}$ by $V_{D S}$ and $I_{C}$ by $I_{D}$ , with $R = R_{D} + R_{S}$ . $P_{D} = I_{C} (V_{C C} - I_{C} R)$ is a parabola in $I_{C}$ that peaks at the midpoint of the load line.

JUNCTION TEMPERATURE

T_{J} = T_{A} + θ_{J A} P_{D}, P_{D, ma x} = \frac{T _{J, ma x} - T _{A}}{θ _{J A}}

$θ_{J A}$ is the thermal resistance from junction to ambient, in °C/W. With a heat sink, $θ_{J A} = θ_{J C} + θ_{C S} + θ_{S A}$ (junction to case, case to sink, sink to ambient).

Thermal runaway. In a BJT, a rise in junction temperature raises $I_{C O}$ and $β$ and lowers $V_{B E}$ , and all three raise $I_{C}$ . If the higher $I_{C}$ increases the dissipation, the junction heats further. The loop runs away, and can destroy the device, unless the heat path removes the extra heat faster than it is produced. A MOSFET biased well above threshold is far less prone to this: carrier mobility falls with temperature, so $I_{D}$ drops as the device heats. Near threshold, the falling $V_{T H}$ can dominate instead, so this protection is not guaranteed there.

CONDITION FOR THERMAL STABILITY

\frac{\partial P _{C}}{\partial T _{J}} = \frac{\partial P _{C}}{\partial I _{C}} \cdot \frac{\partial I _{C}}{\partial T _{J}} < \frac{1}{θ _{J A}}

Dissipation must grow with junction temperature more slowly than the heat path can carry the extra heat away. Low stability factors keep $\partial I_{C} / \partial T_{J}$ small.

SELF-STABILISING Q-POINT

\frac{\partial P _{C}}{\partial I _{C}} = V_{C C} - 2 I_{C} R = 2 V_{C E} - V_{C C} < 0 ⟺ V_{C E} < \frac{V _{C C}}{2}

Here $P_{C} = V_{C E} I_{C}$ with $V_{C E} = V_{C C} - I_{C} R$ and $R = R_{C} + R_{E}$ . With a Q-point below the midpoint of the load line, a rise in $I_{C}$ lowers $P_{C}$ , so runaway cannot start whatever the value of $θ_{J A}$ .

EXAM TIP

The midpoint $V_{C E} = V_{C C} /2$ is both where a symmetric-swing design puts the Q-point and where device dissipation peaks at $V_{C C}^{2} / (4 R)$ . If the Q-point can drift along the load line, rate the transistor against $V_{C C}^{2} / (4 R)$ , not against the Q-point power alone.

PREVIOUS-YEAR QUESTIONS

13 questions from the EC, EE and IN papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2026 · GATE ECE 2025 · GATE ECE 2018 · GATE EE 2024 · GATE EE 2023 · GATE EE 2018 · GATE IN 2026 · GATE IN 2025 · GATE IN 2024 · GATE IN 2022 · GATE IN 2018

GATE 2026 EC Q.18

GATE 2026 · ECQ.18 · 1 mark · MCQ

Consider the circuit shown in the Figure with $V_{i} = 3 V$ and $V_{C C} = 12 V$ .

Assume $V_{B E} = 0.7 V$ and $β_{d c} = 99$ for the BJT.

Which of the following options is the correct value of the current $I_{o}$ ?

GATE 2026 EC question 18: An op-amp whose non-inverting (+) input is driven by the input voltage V_i and whose inverting (−) input is tied by a wire… — Figure from the GATE 2026 EC paper. It is part of the question.

(A)
$60 μ A$
(B)
$6 μ A$
(C)
$3 μ A$
(D)
$30 μ A$

Answer and solution

GATE 2026 EC Q.18: answer and solution

GATE 2026 EC Q.60

GATE 2026 · ECQ.60 · 2 marks · NAT

An $n$ -channel MOSFET is connected as shown in the Figure.

Assume $V_{T H} = 1 V$ , $V_{D D} = 5 V$ , and $μ C_{o x} (\frac{W}{L}) = 2 mA V^{- 2}$ and neglect channel length modulation effects.

The gate voltage $(V_{G})$ of the $n$ -channel MOSFET (in Volt) is ____. (rounded off to two decimal places)

GATE 2026 EC question 60: One n-channel MOSFET, drawn inside a circle, with its drain at the top and its source at the bottom. — Figure from the GATE 2026 EC paper. It is part of the question.

Answer and solution

GATE 2026 EC Q.60: answer and solution

GATE 2026 IN Q.22

GATE 2026 · INQ.22 · 1 mark · MCQ

In the circuit shown, the BJT has a $β$ of 100. The base-emitter junction voltage is 0.65 V. The quiescent collector current, $I_{C}$ is _______ mA.

GATE 2026 IN question 22: Voltage-divider bias of an NPN BJT from a single 5 V supply. — Figure from the GATE 2026 IN paper. It is part of the question.

(A)
0.365
(B)
0.435
(C)
0.625
(D)
0.862

Answer and solution

GATE 2026 IN Q.22: answer and solution

GATE 2025 EC Q.22

GATE 2025 · ECQ.22 · 1 mark · MCQ

The ideal BJT in the circuit given below is biased in the active region with a $β$ of 100.

If $I_{B}$ is $10 μ A$ , then $V_{C E}$ (in Volts, rounded off to two decimal places) is ______ .

GATE 2025 EC question 22: Collector-to-base (collector-feedback) bias circuit with an NPN BJT. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
4.95
(B)
3.03
(C)
1.92
(D)
3.73

Answer and solution

GATE 2025 EC Q.22: answer and solution

GATE 2025 EC Q.47

GATE 2025 · ECQ.47 · 2 marks · MCQ

In the circuit shown, the identical transistors Q1 and Q2 are biased in the active region with $β = 120$ . The Zener diode is in the breakdown region with $V_{Z} = 5 V$ and $I_{Z} = 25 mA$ .

If $I_{L} = 12 mA$ and $V_{E B 1} = V_{E B 2} = 0.7 V$ , then the values of $R_{1}$ and $R_{2}$ (in $k Ω$ , rounded off to one decimal place) are ______, respectively.

GATE 2025 EC question 47: A +20 V supply rail runs across the top. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
0.6 and 0.4
(B)
1.4 and 2.5
(C)
14.0 and 25.0
(D)
6.0 and 4.0

Answer and solution

GATE 2025 EC Q.47: answer and solution

GATE 2025 IN Q.35

GATE 2025 · INQ.35 · 1 mark · NAT

In the circuit shown, assume that the BJT in the circuit has very high $β$ and $V_{B E} = 0.7 V$ , and the Zener diode has $V_{Z} = 4.7 V$ . The current $I$ through the LED is ________ mA (rounded off to two decimal places).

GATE 2025 IN question 35: A supply node V_CC = 12 V at the top feeds a horizontal rail. — Figure from the GATE 2025 IN paper. It is part of the question.

Answer and solution

GATE 2025 IN Q.35: answer and solution

GATE 2024 EE Q.42

GATE 2024 · EEQ.42 · 2 marks · MCQ

A BJT biasing circuit is shown in the figure, where $V_{B E} = 0.7 V$ and $β = 100$ . The Quiescent Point values of $V_{C E}$ and $I_{C}$ are respectively

GATE 2024 EE question 42: Voltage-divider bias circuit with an NPN BJT (emitter arrow pointing outward). — Figure from the GATE 2024 EE paper. It is part of the question.

(A)
4.6 V and 2.46 mA
(B)
3.5 V and 2.46 mA
(C)
2.61 V and 3.13 mA
(D)
4.6 V and 3.13 mA

Answer and solution

GATE 2024 EE Q.42: answer and solution

GATE 2024 IN Q.24

GATE 2024 · INQ.24 · 1 mark · NAT

Figure shows an amplifier using an NMOS transistor. Assume that the transistor is in saturation with device parameters, $μ_{n} C_{o x} = 250 μ A/V^{2}$ , threshold voltage $V_{T} = 0.65 V$ and $W / L = 4$ . Ignore the channel length modulation effect. The drain current of the transistor at the operating point is ________ $μ$ A (rounded off to nearest integer).

GATE 2024 IN question 24: Common-source NMOS amplifier with drain-to-gate feedback bias. — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.24: answer and solution

GATE 2023 EE Q.59

GATE 2023 · EEQ.59 · 2 marks · NAT

The Zener diode in circuit has a breakdown voltage of 5 V. The current gain $β$ of the transistor in the active region in 99. Ignore base-emitter voltage drop $V_{B E}$ . The current through the 20 $Ω$ resistance in milliamperes is ________ (Round off to 2 decimal places).

GATE 2023 EE question 59: A 25 V battery (+ terminal at top) on the left. — Figure from the GATE 2023 EE paper. It is part of the question.

Answer and solution

GATE 2023 EE Q.59: answer and solution

GATE 2022 IN Q.58

GATE 2022 · INQ.58 · 2 marks · NAT

In the circuit shown, $R_{1} = 100 k Ω$ and $R_{2} = 1 k Ω$ . If the base-to-emitter voltage of the npn BJT is $0.7 V$ and the collector-to-emitter voltage is $5.2 V$ , the $β$ (current gain) of the BJT is ________ (round off to two decimal places)

GATE 2022 IN question 58: Collector-feedback bias circuit with an npn BJT. — Figure from the GATE 2022 IN paper. It is part of the question.

Answer and solution

GATE 2022 IN Q.58: answer and solution

GATE 2018 EC Q.43

GATE 2018 · ECQ.43 · 2 marks · NAT

In the circuit shown below, the $(W / L)$ value for $M_{2}$ is twice that for $M_{1}$ . The two nMOS transistors are otherwise identical. The threshold voltage $V_{T}$ for both transistors is 1.0V. Note that $V_{GS}$ for $M_{2}$ must be $> 1.0 V$ .

Current through the nMOS transistors can be modeled as

I_{D S} = μ C_{o x} (\frac{W}{L}) ((V_{GS} - V_{T}) V_{D S} - \frac{1}{2} V_{D S}^{2}) for V_{D S} \leq V_{GS} - V_{T}

I_{D S} = μ C_{o x} (\frac{W}{L}) (V_{GS} - V_{T})^{2} /2 for V_{D S} \geq V_{GS} - V_{T}

The voltage (in volts, accurate to two decimal places) at $V_{x}$ is ______.

GATE 2018 EC question 43: Two enhancement nMOS transistors stacked in series between a 3.3 V supply and ground. — Figure from the GATE 2018 EC paper. It is part of the question.

Answer and solution

GATE 2018 EC Q.43: answer and solution

GATE 2018 EE Q.41

GATE 2018 · EEQ.41 · 2 marks · NAT

In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain $β = 100$ . The base-emitter voltage drop is a constant, $V_{B E} = 0.7 V$ . The value of the Thevenin equivalent resistance $R_{T h}$ (in $Ω$ ) as shown in the figure is ______ (up to 2 decimal places).

GATE 2018 EE question 41: An npn BJT is drawn on its side along the top wire. — Figure from the GATE 2018 EE paper. It is part of the question.

Answer and solution

GATE 2018 EE Q.41: answer and solution

GATE 2018 IN Q.15

GATE 2018 · INQ.15 · 1 mark · NAT

Q.15 In the given circuit, assume that the opamp is ideal and the transistor has a $β$ of 20. The current $I_{o}$ (in $μ$ A) flowing through the load $Z_{L}$ is ______.

GATE 2018 IN question 15: An op-amp drives an NPN transistor. — Figure from the GATE 2018 IN paper. It is part of the question.

Answer and solution

GATE 2018 IN Q.15: answer and solution

PRACTICE

6 questions to test yourself

PRACTICE 11 mark · NAT

An npn transistor with $β = 50$ has its emitter grounded and a collector resistor $R_{C} = 1$ kΩ to $V_{C C} = 5$ V. Its base is driven from a 5 V source through $R_{B} = 20$ kΩ. Take $V_{B E} = 0.7$ V in the active region, and $V_{B E (s a t)} = 0.8$ V and $V_{C E (s a t)} = 0.2$ V in saturation. The collector current, in mA, is ______.

Answer and solution

Answer: $4.8$ (accepted range $\pm 0.02$ )

Assume active: $I_{B} = (5 - 0.7) /20 k = 0.215$ mA, so $I_{C} = 50 \times 0.215 = 10.75$ mA.
Then $V_{C E} = 5 - 10.75 \times 1 = - 5.75$ V, below $V_{C E (s a t)}$ . The active assumption fails.
Assume saturation: $I_{B} = (5 - 0.8) /20 k = 0.21$ mA and $I_{C} = (5 - 0.2) /1 k = 4.8$ mA.
Check: $β_{forced} = 4.8/0.21 = 22.9 < 50$ , so the transistor is saturated and $I_{C} = 4.8$ mA.

PRACTICE 22 marks · NAT

An enhancement NMOS with $V_{T H} = 1$ V, $k_{n} = μ_{n} C_{o x} (W / L) = 1$ mA/V² and $λ = 0$ is biased from $V_{D D} = 12$ V by a gate divider: $R_{1} = 2$ MΩ from $V_{D D}$ to the gate and $R_{2} = 1$ MΩ from the gate to ground. $R_{D} = 5$ kΩ is connected from $V_{D D}$ to the drain and $R_{S} = 2$ kΩ from the source to ground. The source is tied to the body. In saturation, $I_{D} = \frac{1}{2} k_{n} (V_{GS} - V_{T H})^{2}$ . The drain current, in mA, is ______ (to two decimal places).

Answer and solution

Answer: $0.85$ (accepted range $\pm 0.01$ )

$V_{G} = 12 \times 1/ (2 + 1) = 4$ V, since $I_{G} = 0$ .
Bias line (with $I_{D}$ in mA): $V_{GS} = 4 - 2 I_{D}$ . In saturation $I_{D} = 0.5 V_{O V}^{2}$ , so $V_{GS} - V_{T H} = V_{O V}$ gives $3 = V_{O V} + 2 \times 0.5 V_{O V}^{2}$ , i.e. $V_{O V}^{2} + V_{O V} - 3 = 0$ .
$V_{O V} = (- 1 + 13) /2 = 1.303$ V. The other root, $- 2.303$ V, gives $V_{GS} = - 1.30$ V, below $V_{T H}$ , so it is rejected.
$I_{D} = 0.5 \times 1.30 3^{2} = 0.849$ mA, which is 0.85 mA to two decimal places.
Check: $V_{S} = 2 \times 0.849 = 1.70$ V and $V_{D} = 12 - 5 \times 0.849 = 7.76$ V, so $V_{D S} = 6.06$ V, well above $V_{O V} = 1.30$ V. The device is saturated.

PRACTICE 32 marks · NAT

An npn transistor is biased from $V_{C C} = 12$ V by a divider, $R_{1} = 40$ kΩ from $V_{C C}$ to the base and $R_{2} = 10$ kΩ from the base to ground, with $R_{C} = 4$ kΩ and $R_{E} = 1$ kΩ. Take $V_{B E} = 0.7$ V in the active region and neglect leakage. If the transistor is replaced by one with $β = 200$ instead of $β = 100$ , the percentage increase in the collector current is ______ (to one decimal place).

Answer and solution

Answer: $4.3$ (accepted range $\pm 0.1$ )

Thévenin equivalent: $V_{B B} = 12 \times 10/50 = 2.4$ V and $R_{B B} = 40 ∥ 10 = 8$ kΩ.
$β = 100$ : $I_{C 1} = \frac{100 \times 1.7}{8 + 101 \times 1}$ mA $= 1.5596$ mA.
$β = 200$ : $I_{C 2} = \frac{200 \times 1.7}{8 + 201 \times 1}$ mA $= 1.6268$ mA. Then $V_{C E} = 12 - 1.6268 \times 4 - 1.6349 \times 1 = 3.86$ V, so the transistor is still active.
Increase $= (1.6268 - 1.5596) /1.5596 = 0.0431$ , i.e. 4.3%.
Cross-check with the large-change formula: $S_{2} = 201 \times 9/209 = 8.656$ , $S^{''} = 1.5596 \times 8.656/ (100 \times 201) = 0.6716 μ$ A, and $Δ I_{C} = 0.6716 μ A \times 100 = 0.0672$ mA. In fixed bias, doubling $β$ would double $I_{C}$ (a 100% increase).

PRACTICE 41 mark · MCQ

An enhancement PMOS transistor has threshold voltage $V_{T P} = - 0.6$ V and $λ = 0$ . In a circuit its terminal voltages are $V_{S} = 3.3$ V, $V_{G} = 1.8$ V and $V_{D} = 2.0$ V. The region of operation of the transistor is

(A)
cut-off
(B)
triode (linear)
(C)
saturation
(D)
impossible to determine without the value of $k_{p}$

Answer and solution

Answer: (C)

$V_{S G} = 3.3 - 1.8 = 1.5$ V, which exceeds $∣ V_{T P} ∣ = 0.6$ V, so the device is on.
Saturation needs $V_{S D} \geq V_{S G} - ∣ V_{T P} ∣ = 1.5 - 0.6 = 0.9$ V.
$V_{S D} = 3.3 - 2.0 = 1.3$ V, which is at least 0.9 V, so the device is in saturation.
The region depends only on the terminal voltages; $k_{p}$ scales the current and plays no part in the test.

PRACTICE 52 marks · MSQ

Which of the following statements about DC biasing are correct? Assume the constant-drop BJT model and a square-law MOSFET with $λ = 0$ ; leakage $I_{C O}$ is included only where a stability factor is involved.

(A)
In fixed bias (base resistor to $V_{C C}$ , no emitter resistor), the stability factor $S = \partial I_{C} / \partial I_{C O}$ equals $1 + β$ .
(B)
In voltage-divider bias with $R_{B B} = R_{1} ∥ R_{2}$ held fixed, increasing $R_{E}$ decreases the stability factor $S$ .
(C)
An enhancement NMOS with its gate tied to its drain operates in the triode region whenever $V_{GS} > V_{T H}$ .
(D)
For a BJT whose collector-emitter voltage is $V_{C E} = V_{C C} - I_{C} (R_{C} + R_{E})$ (taking $I_{E} \approx I_{C}$ ), a Q-point with $V_{C E} < V_{C C} /2$ means that a small rise in $I_{C}$ reduces the transistor's dissipation $V_{C E} I_{C}$ .

Answer and solution

Answer: (A), (B), (D)

A is correct. In fixed bias $I_{B} = (V_{C C} - V_{B E}) / R_{B}$ does not depend on $I_{C}$ , so $\partial I_{B} / \partial I_{C} = 0$ and $S = (1 + β) / (1 - 0) = 1 + β$ .
B is correct. $S = (1 + β) (R_{B B} + R_{E}) / (R_{B B} + (1 + β) R_{E})$ , and its derivative with respect to $R_{E}$ has numerator $- β (1 + β) R_{B B} < 0$ , so $S$ falls as $R_{E}$ grows.
C is wrong. With the gate tied to the drain, $V_{D S} = V_{GS} > V_{GS} - V_{T H}$ , so the device is always in saturation, never triode.
D is correct. $d P / d I_{C} = V_{C C} - 2 I_{C} (R_{C} + R_{E}) = 2 V_{C E} - V_{C C}$ , which is negative when $V_{C E} < V_{C C} /2$ .

PRACTICE 62 marks · MCQ

In a collector-to-base bias circuit, an npn transistor ( $β = 100$ , $V_{B E} = 0.7$ V) has $R_{C} = 2$ kΩ from $V_{C C} = 10$ V to the collector, $R_{B} = 200$ kΩ from the collector to the base, and its emitter grounded. The collector-emitter voltage $V_{C E}$ is closest to

(A)
5.33 V
(B)
5.37 V
(C)
0.70 V
(D)
0.20 V

Answer and solution

Answer: (A)

KVL from $V_{C C}$ through $R_{C}$ and $R_{B}$ to the base: $V_{C C} = (I_{C} + I_{B}) R_{C} + I_{B} R_{B} + V_{B E} = (β + 1) I_{B} R_{C} + I_{B} R_{B} + V_{B E}$ .
$I_{B} = (10 - 0.7) / (200 + 101 \times 2) k = 9.3/402 k = 23.13 μ$ A, so $I_{C} = 2.313$ mA and $I_{E} = 2.337$ mA.
$V_{C E} = V_{C C} - I_{E} R_{C} = 10 - 2.337 \times 2 = 5.33$ V.
B comes from finding $I_{B}$ correctly but then charging $R_{C}$ with $I_{C}$ alone: $10 - 2.313 \times 2 = 5.37$ V. C comes from treating the circuit as fixed bias ( $R_{B}$ returned to $V_{C C}$ ): $I_{B} = 9.3/200 k = 46.5 μ$ A, $I_{C} = 4.65$ mA, $V_{C E} = 10 - 9.3 = 0.70$ V. D is impossible: $V_{C B} = I_{B} R_{B} > 0$ , so this circuit cannot saturate.

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