GATE EC · EE · IN

Diode circuits

Clipping, clamping, rectifiers and regulators

Diode circuits use the diode's one-way conduction to shape waveforms and supply power: clippers limit a waveform, clampers shift it, rectifiers and filters turn ac into dc, multipliers raise the dc level, and Zener regulators hold it steady. Nearly every problem here comes down to one skill: decide which diodes are ON, replace each with the model the data calls for (ideal, constant-drop or piecewise-linear), and solve the linear circuit that remains. The rest is a short set of rectifier, filter and regulator results, and each one depends on stated conditions such as the diode model, a resistive or capacitive load, and which peak voltage V_m refers to.

25 previous-year questions · 25 solved · 7 practice questions

Diode models and the method of assumed states

A diode conducts easily when its anode is more positive than its cathode by about the cut-in voltage $V_{γ}$ . When reverse-biased (below breakdown) it blocks, to a first approximation. Every circuit in this topic is solved by replacing each diode with a straight-line model that is valid in its present state. So the first decision in any question is which model the data asks for, and the second is which state each diode is in.

SHOCKLEY DIODE EQUATION

I_{D} = I_{S} (e^{V_{D} / (n V_{T})} - 1), V_{T} = \frac{k T}{q}

Exponential model of the junction below breakdown (series resistance neglected). $I_{S}$ = reverse saturation current, $n$ = ideality factor (1 to 2). $V_{T} = 25.9$ mV at 300 K; these notes round it to 25 mV, and 26 mV is also common, so take the value the question gives. For $V_{D} ≫ n V_{T}$ , $I_{D} \approx I_{S} e^{V_{D} / (n V_{T})}$ ; for $V_{D} ≪ - V_{T}$ , $I_{D} \approx - I_{S}$ .

FORWARD VOLTAGE CHANGE WITH CURRENT

V_{D 2} - V_{D 1} = n V_{T} ln \frac{I _{D 2}}{I _{D 1}} = 2.303 n V_{T} lo g_{10} \frac{I _{D 2}}{I _{D 1}}

Valid when both currents are much larger than $I_{S}$ . With $n = 1$ and $V_{T} = 25$ mV, a tenfold change in current changes $V_{D}$ by 57.6 mV (about 60 mV with 26 mV).

DYNAMIC (SMALL-SIGNAL) RESISTANCE

r_{d} = \frac{n V _{T}}{I _{D}}

Slope resistance $d V_{D} / d I_{D}$ at the dc operating current $I_{D}$ (valid for $I_{D} ≫ I_{S}$ ), used when a small ac signal rides on a dc bias. With $n = 1$ , $V_{T} = 25$ mV and $I_{D} = 1$ mA, $r_{d} = 25 Ω$ .

TEMPERATURE DEPENDENCE (SILICON, NEAR ROOM TEMPERATURE)

\frac{d V _{D}}{d T} \approx - 2 mV /^{\circ} C (constant I_{D}), I_{S} (T_{2}) \approx I_{S} (T_{1}) 2^{(T_{2} - T_{1}) /10} (T in^{\circ} C)

At a fixed current the forward drop falls as temperature rises (figures between about $- 2$ and $- 2.5$ mV/°C are quoted, so use the value given). Problems often assume the reverse saturation current doubles for every 10 °C rise (about 7% per °C). This is a rule of thumb: some treatments give a faster rate for the ideal-junction $I_{S}$ , so if a question states a rate, use it.

Model	When ON (conducting)	When OFF	Use it when
Ideal	Short circuit: $V_{D} = 0$ , any $I_{D} \geq 0$	Open circuit: any $V_{D} \leq 0$	The question says ideal, or the source voltages are far larger than 0.7 V
Constant-drop	Battery $V_{D} = V_{γ}$ (0.7 V Si, about 0.3 V Ge), $I_{D} \geq 0$	Open circuit: $V_{D} < V_{γ}$	A cut-in or forward voltage is given and no resistance
Piecewise-linear	$V_{γ}$ in series with $r_{f}$ : $V_{D} = V_{γ} + I_{D} r_{f}$	Open circuit (or a reverse resistance $r_{r}$ if one is given)	A forward resistance $r_{f}$ is given
Exponential	$I_{D} = I_{S} (e^{V_{D} / (n V_{T})} - 1)$	$I_{D} \approx - I_{S}$	$I_{S}$ is given, or a small-signal $r_{d}$ is needed

Method of assumed states

Guess a state (ON or OFF) for every diode, usually from the direction in which the source pushes current.
Replace each ON diode by its model (short, $V_{γ}$ battery, or $V_{γ}$ plus $r_{f}$ ) and each OFF diode by an open circuit.
Solve the resulting linear circuit.
Verify: every ON diode must carry $I_{D} \geq 0$ from anode to cathode; every OFF diode must have $V_{D} < V_{γ}$ ( $V_{D} \leq 0$ for the ideal model).
If a check fails, change that diode's state and solve again. With several diodes, change one at a time, starting with the most clearly violated.
For a time-varying input, find the breakpoints: the input values at which a diode changes state ( $I_{D} = 0$ and $V_{D} = V_{γ}$ at the same time). Between breakpoints the circuit is linear, so the transfer characteristic $v_{o}$ against $v_{i}$ is a set of straight segments.

EXAM TIP

Use exactly the model the data implies. If the question says ideal, do not subtract 0.7 V; if it gives a cut-in voltage, do not ignore it. An answer worked with the wrong model is still a reasonable-looking number, so it will not look wrong.

EXAM TIP

Suppose two diodes connect one node to different voltages, or have different cut-in voltages. The diode that turns on first fixes the node voltage and can hold the other OFF. Check this with assumed states rather than assuming both conduct.

Clippers (limiters)

A clipper passes the part of the input on one side of a reference level and removes the part beyond it, without changing the shape of the rest. In a series clipper the diode sits between the input and the load; with the output taken across $R_{L}$ alone, the output is zero whenever the diode is OFF. In a shunt (parallel) clipper a series resistor $R$ feeds the output node, and the diode with its bias battery sits across the output. When the diode is OFF the output follows the input (exactly, when there is no load); when it is ON the output is pinned at the bias level plus or minus $V_{γ}$ .

The reliable method is the transfer characteristic: find each breakpoint, draw $v_{o}$ against $v_{i}$ as straight segments, then read off the output for the given input waveform. The shunt-clipper results below assume no load (or $R_{L} ≫ R$ ) and the constant-drop model; for an ideal diode, set $V_{γ} = 0$ . Sign convention for shunt clippers and clampers: $V_{R}$ is the signed potential, relative to ground, of the diode terminal that is not connected to the output node. A 3 V battery with its positive terminal to the diode and its negative terminal grounded gives $V_{R} = + 3$ V; the same battery reversed gives $V_{R} = - 3$ V.

UPPER-LEVEL SHUNT CLIPPER

v_{o} = min (v_{i}, V_{R} + V_{γ})

Diode anode at the output node, cathode at potential $V_{R}$ . The diode conducts, and the output is flat, for $v_{i} \geq V_{R} + V_{γ}$ .

LOWER-LEVEL SHUNT CLIPPER

v_{o} = max (v_{i}, V_{R} - V_{γ})

Diode cathode at the output node, anode at potential $V_{R}$ . The diode conducts for $v_{i} \leq V_{R} - V_{γ}$ . With the anode at $- 5$ V, for example, the output cannot fall below $- 5.7$ V.

DOUBLE-ENDED (TWO-LEVEL) CLIPPER

v_{o} = min (max (v_{i}, V_{2} - V_{γ}), V_{1} + V_{γ})

Two shunt branches: an upper-level diode with its cathode at potential $V_{1}$ , and a lower-level diode with its anode at potential $V_{2}$ , where $V_{2} - V_{γ} < V_{1} + V_{γ}$ . The output is confined to $V_{2} - V_{γ} \leq v_{o} \leq V_{1} + V_{γ}$ , and at most one diode conducts at any instant. Two identical Zener diodes connected back to back in series (anode to anode, or cathode to cathode) across the output, fed through a series resistor, clip at $\pm (V_{Z} + V_{γ})$ : on each half-cycle one is in breakdown and the other is forward-biased.

TRANSFER-CHARACTERISTIC SLOPES WITH A LOAD

unclipped: \frac{R _{L}}{R + R _{L}}, clipped: \frac{r _{f} ∥ R _{L}}{R + r _{f} ∥ R _{L}}

Shunt clipper with series resistor $R$ , load $R_{L}$ and diode forward resistance $r_{f}$ (piecewise-linear model). The breakpoint moves to $v_{i} = V_{clip} (R + R_{L}) / R_{L}$ , where $V_{clip} = V_{R} + V_{γ}$ (upper-level) or $V_{R} - V_{γ}$ (lower-level). With $r_{f} = 0$ the clipped region is flat; with $R_{L} \to \infty$ the unclipped slope is 1.

Configuration (constant-drop diode; shunt rows unloaded)	Diode ON when	$v_{o}$ when ON	$v_{o}$ when OFF
Series, anode toward the input, output across $R_{L}$	$v_{i} > V_{γ}$	$v_{i} - V_{γ}$	0
Series, with a battery $V_{B}$ in the loop opposing conduction, output across $R_{L}$ alone	$v_{i} > V_{B} + V_{γ}$	$v_{i} - V_{B} - V_{γ}$	0
Shunt, anode to output, cathode at $V_{R}$	$v_{i} \geq V_{R} + V_{γ}$	$V_{R} + V_{γ}$	$v_{i}$
Shunt, cathode to output, anode at $V_{R}$	$v_{i} \leq V_{R} - V_{γ}$	$V_{R} - V_{γ}$	$v_{i}$

WORKED EXAMPLE

In a shunt clipper, $v_{i} = 10 sin ω t$ V drives a series $1 k Ω$ resistor that feeds the output node (no load). Two branches run from the output node to ground. D1 has its anode at the output and its cathode at the positive terminal of a 3 V battery whose negative terminal is grounded. D2 has its cathode at the output and its anode at the negative terminal of a 5 V battery whose positive terminal is grounded. Using the constant-drop model with $V_{γ} = 0.7$ V, find (a) the limits of $v_{o}$ , (b) the fraction of each cycle for which D1 conducts, and (c) the peak current in D2.

Solution

D1's cathode is at $V_{R} = + 3$ V, so D1 is ON when $v_{o} - 3 \geq 0.7$ , i.e. $v_{o} \geq 3.7$ V. D2's anode is at $V_{R} = - 5$ V, so D2 is ON when $- 5 - v_{o} \geq 0.7$ , i.e. $v_{o} \leq - 5.7$ V. Both cannot conduct at once.
With both diodes OFF no current flows in the resistor, so $v_{o} = v_{i}$ for $- 5.7 < v_{i} < 3.7$ V. Beyond either breakpoint the ON diode pins the output, so $v_{o}$ stays between $- 5.7$ V and $+ 3.7$ V.
D1 conducts while $10 sin θ \geq 3.7$ , from $θ_{1} = sin^{- 1} (0.37) = 21. 7^{\circ}$ to $18 0^{\circ} - 21. 7^{\circ} = 158. 3^{\circ}$ . That is $136. 6^{\circ}$ out of $36 0^{\circ}$ .
Fraction of the cycle $= 136.6/360 = 0.379$ .
D2's current peaks at $v_{i} = - 10$ V: $i = \frac{- 5.7 - ( - 10 )}{1 k Ω} = 4.3$ mA. It flows through D2 from its anode (at $- 5$ V) into the output node, then through the resistor towards the source.

Answer: $- 5.7 V \leq v_{o} \leq + 3.7 V$ ; D1 conducts for 37.9% of each cycle; D2's peak current is 4.3 mA.

EXAM TIP

A clipper changes the waveform's peak-to-peak value whenever it actually clips; a clamper does not. An output option with the same shape and peak-to-peak value as the input, only shifted, points to a series capacitor: the circuit is a clamper, not a clipper.

EXAM TIP

Reversing the diode in a shunt clipper moves the flat part to the other side of the reference; reversing the battery changes the sign of $V_{R}$ . Get the ON condition from the diode's own terminals, $V_{anode} - V_{cathode} \geq V_{γ}$ , rather than from a memorised picture.

Clampers (level shifters)

A clamper (dc restorer) shifts the whole waveform up or down without changing its shape. It consists of a series capacitor $C$ feeding the output, a diode in shunt (optionally with a bias battery, the diode's other terminal then sitting at potential $V_{R}$ as defined for clippers), and a load $R_{L}$ across the output. During the first cycle or two the diode conducts at one peak and charges $C$ . Once $C$ is charged, the diode only just reaches conduction at that peak, so in steady state $v_{o} = v_{i} + V_{shift}$ with $V_{shift}$ constant. This needs $R_{L} C ≫ T$ , so that $C$ loses negligible charge between peaks.

Finding the steady-state output

Find the level the diode enforces when ON. With the anode at the output and the cathode at potential $V_{R}$ , the output cannot rise above $V_{clamp} = V_{R} + V_{γ}$ : the top of the waveform is pinned (a negative clamper when $V_{R} = 0$ ). With the cathode at the output and the anode at potential $V_{R}$ , the output cannot fall below $V_{clamp} = V_{R} - V_{γ}$ : the bottom is pinned (a positive clamper when $V_{R} = 0$ ). $V_{R}$ is the signed potential defined in the clipper section.
In steady state the input peak on the pinned side lands exactly on $V_{clamp}$ . That fixes $V_{shift}$ .
Write $v_{o} = v_{i} + V_{shift}$ and read off the other peak.
Check that the output peak-to-peak equals the input peak-to-peak.

TOP-PINNED CLAMPER (DIODE ANODE AT OUTPUT)

V_{shift} = V_{R} + V_{γ} - V_{i, m a x}, v_{o} = v_{i} + V_{shift}

Diode anode at the output, cathode at potential $V_{R}$ . The capacitor settles at $V_{C} = V_{i, m a x} - (V_{R} + V_{γ})$ , input-side plate positive. Unbiased ideal case: $v_{o} = v_{i} - V_{m}$ , so the output runs from $0$ to $- 2 V_{m}$ .

BOTTOM-PINNED CLAMPER (DIODE CATHODE AT OUTPUT)

V_{shift} = V_{R} - V_{γ} - V_{i, m i n}, v_{o} = v_{i} + V_{shift}

Diode cathode at the output, anode at potential $V_{R}$ . For a sinusoid, $V_{i, m i n} = - V_{m}$ . Unbiased ideal case: $v_{o} = v_{i} + V_{m}$ , so the output runs from $0$ to $2 V_{m}$ .

CLAMPER CONDITIONS AND DC VALUE

R_{L} C ≫ T, V_{o, pp} = V_{i, pp}, V_{o, dc} = V_{i, dc} + V_{shift}

$V_{shift}$ is found from the actual input peaks and $V_{i, dc}$ is the input's average. For a zero-mean input such as a sinusoid, $V_{o, dc} = V_{shift}$ . For a square wave, the time constant must be much larger than the interval during which the diode is OFF.

PEAK REVERSE VOLTAGE ON A CLAMPER DIODE

V_{D, rev,max} = ∣ v_{o, far peak} - V_{R} ∣ (= 2 V_{m} for an unbiased ideal clamper)

The far peak is the output peak on the side opposite the pinned one; $V_{R}$ is the signed potential of the diode's other terminal.

WORKED EXAMPLE

$v_{i} = 8 sin ω t$ V is applied through a series capacitor $C$ to the output node. From the output node to ground there is a diode with its anode at the output and its cathode at the positive terminal of a 2 V battery (negative terminal grounded), and a load $R_{L}$ with $R_{L} C ≫ T$ . With the constant-drop model ( $V_{γ} = 0.7$ V), find the steady-state output extremes, the capacitor voltage, the average output, and the maximum reverse voltage across the diode.

Solution

The cathode is at $V_{R} = + 2$ V, and the diode conducts when $v_{o} - 2 \geq 0.7$ , so the output can never exceed $V_{clamp} = 2.7$ V. The top of the waveform is pinned.
At the input's positive peak (8 V) the output sits at 2.7 V, so $V_{shift} = 2.7 - 8 = - 5.3$ V. The capacitor holds 5.3 V, input-side plate positive.
$v_{o} = v_{i} - 5.3$ V, with maximum $+ 2.7$ V and minimum $- 8 - 5.3 = - 13.3$ V. The peak-to-peak is 16 V, the same as the input.
Average output $= V_{shift} = - 5.3$ V, since the sine averages to zero.
The diode's reverse voltage is largest at the output's negative peak: cathode at $+ 2$ V, anode at $- 13.3$ V, giving $2 - (- 13.3) = 15.3$ V.

Answer: $v_{o}$ swings from $+ 2.7$ V to $- 13.3$ V; $V_{C} = 5.3$ V; average output $- 5.3$ V; maximum diode reverse voltage 15.3 V.

EXAM TIP

You can tell the pinned side from the diode alone: the output can never go past the level at which the diode would become forward-biased. A diode pointing away from the output node (anode at the output) pins the top. A diode pointing into the output node (cathode at the output) pins the bottom.

EXAM TIP

If $R_{L} C$ is not much larger than $T$ , the capacitor discharges between peaks, the output tilts, and the simple shift result no longer holds. A question that intends the simple result states or implies a large time constant.

Rectifiers: half-wave, centre-tapped and bridge

A rectifier converts ac into unidirectional (pulsating dc) output. In this section $V_{m}$ is the peak voltage of the transformer secondary; for a centre-tapped transformer it is the peak of each half of the secondary. The load is a resistor $R_{L}$ and the diodes are ideal unless stated. The half-wave circuit uses one diode. The centre-tapped full-wave circuit uses two, one per half-cycle. The bridge uses four, with two in series in the current path on each half-cycle.

DEFINITIONS: DC VALUE, FORM FACTOR, RIPPLE FACTOR

V_{dc} = \frac{1}{T} \int_{0}^{T} v_{o} d t, FF = \frac{V _{rms}}{V _{dc}}, RF = \frac{V _{r, rms}}{V _{dc}} = FF^{2} - 1

These apply to any periodic output. $V_{r, rms} = V_{rms}^{2} - V_{dc}^{2}$ is the rms value of the ac part alone.

HALF-WAVE RECTIFIER (IDEAL DIODE, RESISTIVE LOAD)

V_{dc} = \frac{V _{m}}{π}, V_{rms} = \frac{V _{m}}{2}, FF = \frac{π}{2} = 1.57, RF = 1.21

Currents follow the same ratios, with $I_{m} = V_{m} / R_{L}$ . The ripple fundamental is at $f$ , and PIV $= V_{m}$ .

FULL-WAVE RECTIFIER (CENTRE-TAPPED OR BRIDGE, IDEAL DIODES)

V_{dc} = \frac{2 V _{m}}{π}, V_{rms} = \frac{V _{m}}{2}, FF = \frac{π}{2 2} = 1.11, RF = 0.483

The ripple fundamental is at $2 f$ . PIV $= 2 V_{m}$ for the centre-tapped circuit and $V_{m}$ for the bridge.

FOURIER SERIES OF THE RECTIFIED OUTPUT

v_{HW} (t) = \frac{V _{m}}{π} + \frac{V _{m}}{2} sin ω t - \frac{2 V _{m}}{π} k = 1 \sum \infty \frac{cos 2 k ω t}{4 k ^{2} - 1}, v_{FW} (t) = \frac{2 V _{m}}{π} - \frac{4 V _{m}}{π} k = 1 \sum \infty \frac{cos 2 k ω t}{4 k ^{2} - 1}

Ideal diodes, resistive load, input $V_{m} sin ω t$ with $ω = 2 π f$ . The half-wave output contains the fundamental $f$ plus even harmonics. The full-wave output contains only even harmonics; the largest is at $2 f$ , with amplitude $4 V_{m} / (3 π)$ .

RECTIFICATION EFFICIENCY

η = \frac{I _{dc}^{2} R _{L}}{I _{rms}^{2} ( R _{L} + R _{f} )} : η_{HW} = \frac{4}{π ^{2}} \cdot \frac{R _{L}}{R _{L} + R _{f}}, η_{FW} = \frac{8}{π ^{2}} \cdot \frac{R _{L}}{R _{L} + R _{f}}

dc load power divided by the ac power fed to the rectifier. $R_{f}$ is the total diode forward resistance in the conduction path: $r_{f}$ for half-wave and centre-tapped, $2 r_{f}$ for the bridge. Add winding resistance if it is given. The maxima (ideal diodes) are $4/ π^{2} = 40.5%$ and $8/ π^{2} = 81.1%$ . The figures 40.6% and 81.2% also appear; treat them as the same result.

RECTIFIERS WITH DIODE AND WINDING RESISTANCE

I_{m} = \frac{V _{m}}{R _{s} + R _{f} + R _{L}}, V_{dc} = V_{dc,NL} - I_{dc} (R_{s} + R_{f}), % regulation = \frac{V _{N L} - V _{F L}}{V _{F L}} \times 100 = \frac{R _{s} + R _{f}}{R _{L}} \times 100

Diodes modelled as ideal switches with forward resistance $r_{f}$ (no cut-in voltage). $R_{f} = r_{f}$ for half-wave and centre-tapped, $2 r_{f}$ for the bridge. $R_{s}$ is the secondary winding resistance (one half-winding for centre-tapped). $V_{dc,NL} = V_{m} / π$ (half-wave) or $2 V_{m} / π$ (full-wave), and $I_{dc} = I_{m} / π$ or $2 I_{m} / π$ respectively.

TRANSFORMER UTILISATION FACTOR

TUF = \frac{P _{dc}}{VA rating of the secondary}

Ideal diodes, resistive load. Half-wave: $22 / π^{2} \approx 0.287$ . Bridge: $8/ π^{2} \approx 0.81$ . Centre-tapped: $\approx 0.57$ for the secondary and $0.81$ for the primary; the 0.69 in the table below is the average of the two. A lower TUF means a larger transformer for the same dc power. In the half-wave circuit the secondary also carries a dc current, which can saturate the core.

RECTIFIERS WITH CONSTANT-DROP DIODES

V_{m, out} = V_{m} - V_{γ} (HW, CT), V_{m, out} = V_{m} - 2 V_{γ} (bridge)

Use the peak output in place of $V_{m}$ in the $V_{dc}$ formula, e.g. $V_{dc} \approx (V_{m} - V_{γ}) / π$ for half-wave. This approximation slightly overestimates $V_{dc}$ , because the diode actually conducts for less than a half-cycle. To first order in $V_{γ} / V_{m}$ , the half-wave average is $V_{m} / π - V_{γ} /2$ . PIV becomes $V_{m}$ (half-wave), $2 V_{m} - V_{γ}$ (centre-tapped) and $V_{m} - V_{γ}$ (bridge).

Quantity (ideal diodes, $R_{L}$ load)	Half-wave	Full-wave centre-tapped	Full-wave bridge
Diodes / conducting at a time	1 / 1	2 / 1	4 / 2
$V_{dc}$	$V_{m} / π = 0.318 V_{m}$	$2 V_{m} / π = 0.637 V_{m}$	$2 V_{m} / π = 0.637 V_{m}$
$V_{rms}$	$V_{m} /2$	$V_{m} / 2$	$V_{m} / 2$
Form factor	1.57	1.11	1.11
Peak factor $V_{m} / V_{rms}$	2	$2$	$2$
Ripple factor	1.21	0.483	0.483
Maximum efficiency	$4/ π^{2} \approx 40.5%$	$8/ π^{2} \approx 81.1%$	$8/ π^{2} \approx 81.1%$
PIV per diode	$V_{m}$	$2 V_{m}$	$V_{m}$
TUF	0.287	0.69 (average)	0.81
Ripple fundamental	$f$	$2 f$	$2 f$
Peak output, constant-drop	$V_{m} - V_{γ}$	$V_{m} - V_{γ}$	$V_{m} - 2 V_{γ}$

EXAM TIP

The centre-tapped PIV is $2 V_{m}$ , not $V_{m}$ : while one diode conducts, the other has the whole secondary (both halves) across it. The bridge needs four diodes, but each withstands only $V_{m}$ and no centre tap is needed.

EXAM TIP

A half-wave ripple factor above 1 is correct: the output's ac content exceeds its dc value. Rectification efficiency compares dc load power with the ac power delivered to the rectifier; it is not the transformer's efficiency.

Capacitor and inductor filters, peak detectors and voltage multipliers

A capacitor $C$ across the load turns the rectifier into a peak detector. The capacitor charges through the diode to the peak output, then discharges through $R_{L}$ while the input falls and the diode is OFF. The diode turns on again only when the rising input exceeds the capacitor voltage. So it conducts for a short conduction angle near each peak and delivers all the load charge in short, tall current pulses. Here $V_{m}$ is the peak output voltage (after diode drops) and $V_{r}$ the peak-to-peak ripple; the results assume $V_{r} ≪ V_{m}$ , i.e. $R_{L} C ≫ T$ .

PEAK-TO-PEAK RIPPLE

V_{r} \approx \frac{V _{m}}{f R _{L} C} = \frac{I _{dc}}{f C} (half-wave), V_{r} \approx \frac{V _{m}}{2 f R _{L} C} = \frac{I _{dc}}{2 f C} (full-wave)

Assumes the capacitor discharges at a constant current $I_{dc} \approx V_{m} / R_{L}$ for the full period $T$ (half-wave) or $T /2$ (full-wave), neglecting the conduction interval. This standard approximation slightly overestimates the ripple.

DC OUTPUT WITH A CAPACITOR FILTER

V_{dc} \approx V_{m} - \frac{V _{r}}{2}

Treats the ripple as a triangle between $V_{m}$ and $V_{m} - V_{r}$ .

RIPPLE FACTOR WITH A CAPACITOR FILTER

RF \approx \frac{V _{r}}{2 3 V _{dc}} \approx \frac{1}{2 3 f R _{L} C} (HW), \frac{1}{4 3 f R _{L} C} (FW)

A triangular ripple of peak-to-peak $V_{r}$ has rms value $V_{r} / (23)$ . The last two forms take $V_{dc} \approx V_{m}$ .

CONDUCTION ANGLE

Δ θ = cos^{- 1} (1 - \frac{V _{r}}{V _{m}}) \approx \frac{2 V _{r}}{V _{m}} rad

Angle of each charging pulse, measured from diode turn-on to the peak. Smaller ripple gives a shorter pulse and a larger peak diode current.

AVERAGE DIODE CURRENT DURING CONDUCTION (CHARGE BALANCE)

i_{D, av} \approx I_{L} (1 + π \frac{2 V _{m}}{V _{r}}) (HW), i_{D, av} \approx I_{L} (1 + π \frac{V _{m}}{2 V _{r}}) (FW)

During its short conduction interval the diode supplies the charge the capacitor lost in one discharge interval, plus the load current for the interval itself. The small-angle conduction angle above is used. The peak diode current, estimated at turn-on from $i_{C} = C d v / d t$ , is about $I_{L} (1 + 2 π 2 V_{m} / V_{r})$ (HW) or $I_{L} (1 + 2 π V_{m} / (2 V_{r}))$ (FW).

PIV WITH A CAPACITOR FILTER

PIV = 2 V_{m} (half-wave and centre-tapped), PIV = V_{m} (bridge)

Ideal diodes. Here $V_{m}$ is the secondary peak (each half, for centre-tapped), which with ideal diodes equals the peak output. In the half-wave case the capacitor holds $+ V_{m}$ on the cathode while the anode swings to $- V_{m}$ , so the PIV is double the resistive-load value. With constant-drop diodes these become $2 V_{m} - V_{γ}$ (half-wave and centre-tapped) and $V_{m} - V_{γ}$ (bridge).

INDUCTOR AND LC FILTERS (FULL-WAVE)

L: RF = \frac{2}{3 1 + 4 ω ^{2} L ^{2} / R _{L}^{2}} \approx \frac{R _{L}}{3 2 ω L}, LC: RF \approx \frac{1}{6 2 ω ^{2} L C}, L_{c} = \frac{R _{L}}{3 ω}

Full-wave rectifier, $ω = 2 π f$ of the supply, lossless inductor, and only the $2 ω$ ripple term (amplitude $4 V_{m} /3 π$ ) kept. The L-filter approximation needs $2 ω L ≫ R_{L}$ . The LC result needs $1/ (2 ω C) ≪ R_{L}$ and $2 ω L ≫ 1/ (2 ω C)$ . $L_{c}$ is the critical inductance of the LC filter: with $L \geq L_{c}$ the inductor current never falls to zero, and $V_{dc} \approx 2 V_{m} / π$ . An inductor filter smooths better with a heavier load (smaller $R_{L}$ ), the opposite of a capacitor filter.

Peak detector. A half-wave rectifier with a capacitor and a very large $R_{L} C$ holds the peak of its input: $V_{o} \approx V_{m} - V_{γ}$ with the constant-drop model, or $V_{m}$ with an ideal diode. A larger $R_{L} C$ holds the peak longer but follows a falling envelope more slowly.

VOLTAGE DOUBLER AND MULTIPLIER (NO LOAD, IDEAL DIODES)

V_{o} = 2 V_{m} (doubler), V_{o} = n V_{m} (n -stage multiplier)

Half-wave doubler: a clamper ( $C_{1}$ charges to $V_{m}$ ) followed by a peak detector that captures the clamped waveform's $2 V_{m}$ peak. Its ripple is at $f$ , each diode sees a PIV of $2 V_{m}$ , and $C_{1}$ is rated $V_{m}$ while $C_{2}$ is rated $2 V_{m}$ . Full-wave doubler: two peak detectors that charge on alternate half-cycles, stacked in series, with ripple at $2 f$ . Cascading more clamper–detector sections gives $3 V_{m}$ , $4 V_{m}$ and so on. Under load the output falls below these values.

WORKED EXAMPLE

A bridge rectifier with a capacitor-input filter is fed from a 15 V (rms), 50 Hz transformer secondary. The diodes follow the constant-drop model with $V_{γ} = 0.7$ V; $R_{L} = 500 Ω$ and $C = 1000 μ$ F. Estimate the peak output, peak-to-peak ripple, dc output, ripple factor, conduction angle and diode PIV.

Solution

Secondary peak $= 152 = 21.21$ V. Two diodes conduct in series, so the peak output is $V_{m} = 21.21 - 1.4 = 19.81$ V.
Full-wave ripple: $V_{r} \approx \frac{V _{m}}{2 f R _{L} C} = \frac{19.81}{2 \times 50 \times 500 \times 1 0 ^{- 3}} = \frac{19.81}{50} = 0.396$ V.
$V_{dc} \approx V_{m} - V_{r} /2 = 19.81 - 0.20 = 19.61$ V.
Ripple factor $\approx \frac{V _{r}}{2 3 V _{dc}} = \frac{0.396}{3.464 \times 19.61} = 0.0058$ , i.e. 0.58%.
Conduction angle $\approx 2 V_{r} / V_{m} = 2 \times 0.396/19.81 = 0.200$ rad $\approx 11. 5^{\circ}$ per half-cycle.
PIV: while one pair conducts, each OFF diode sees the secondary peak less one diode drop, $21.21 - 0.7 = 20.5$ V.

Answer: $V_{m} \approx 19.8$ V, $V_{r} \approx 0.40$ V, $V_{dc} \approx 19.6$ V, ripple factor $\approx 0.0058$ , conduction angle $\approx 11. 5^{\circ}$ , PIV $\approx 20.5$ V.

EXAM TIP

Doubling $C$ halves the ripple but shortens the conduction angle, so the diode's current pulses get taller. Capacitor-input filters load the diodes and the transformer with high peak currents.

EXAM TIP

Check which peak a formula means. The ripple formulas use the peak output (after diode drops); PIV uses the secondary peak.

Zener diode shunt regulator

A Zener diode biased into reverse breakdown holds a nearly constant voltage $V_{Z}$ over a wide current range. In the shunt regulator, a series resistor $R$ from the unregulated supply $V_{S}$ feeds the output node, with the Zener and the load $R_{L}$ in parallel across the output. $R$ drops the difference between $V_{S}$ and $V_{Z}$ , and the Zener takes whatever current the load does not. The circuit regulates only while $I_{Z, m i n} \leq I_{Z} \leq I_{Z, m a x}$ , where $I_{Z, m i n}$ is the knee current and $I_{Z, m a x} = P_{Z, m a x} / V_{Z}$ .

Analysis procedure

Breakdown check: remove the Zener and find the open-circuit output $V_{S} R_{L} / (R + R_{L})$ . If it is below $V_{Z}$ , the Zener is OFF (an open circuit) and the output is simply this divider voltage.
Otherwise replace the Zener by a battery $V_{Z}$ , so $V_{o} = V_{Z}$ . If $r_{z}$ is given, use $V_{Z 0}$ in series with $r_{z}$ instead, so $V_{o} = V_{Z 0} + r_{z} I_{Z}$ .
Compute $I_{R} = (V_{S} - V_{Z}) / R$ , $I_{L} = V_{Z} / R_{L}$ and $I_{Z} = I_{R} - I_{L}$ .
Check $I_{Z, m i n} \leq I_{Z} \leq I_{Z, m a x}$ and find $P_{Z} = V_{Z} I_{Z}$ .

ZENER MODEL IN BREAKDOWN

V_{Z} = V_{Z 0} + r_{z} I_{Z}

Piecewise-linear model, with $r_{z}$ the Zener (dynamic) resistance. With $r_{z} = 0$ the output is exactly $V_{Z}$ .

REGULATOR CURRENTS

I_{R} = \frac{V _{S} - V _{Z}}{R}, I_{L} = \frac{V _{Z}}{R _{L}}, I_{Z} = I_{R} - I_{L}

Valid only while the Zener is in breakdown.

BREAKDOWN CONDITION

\frac{V _{S} R _{L}}{R + R _{L}} \geq V_{Z}

If this fails, the Zener is OFF and $V_{o} = V_{S} R_{L} / (R + R_{L})$ .

LOAD LIMITS FOR FIXED V_S AND R

I_{L, m a x} = I_{R} - I_{Z, m i n}, R_{L, m i n} = \frac{V _{Z}}{I _{R} - I _{Z, m i n}} (= \frac{V _{Z} R}{V _{S} - V _{Z}} if I_{Z, m i n} = 0)

A heavier load (smaller $R_{L}$ ) takes current away from the Zener, and below $R_{L, m i n}$ the Zener drops out of breakdown. At the other end, $I_{L, m i n} = I_{R} - I_{Z, m a x}$ . If that is zero or negative, running with no load is safe.

SERIES-RESISTOR DESIGN RANGE

\frac{V _{S, m a x} - V _{Z}}{I _{Z, m a x} + I _{L, m i n}} \leq R \leq \frac{V _{S, m i n} - V _{Z}}{I _{Z, m i n} + I _{L, m a x}}

Upper limit: at minimum input and maximum load, the Zener must still get $I_{Z, m i n}$ . Lower limit: at maximum input and minimum load, the Zener must not exceed $I_{Z, m a x}$ . If the lower limit comes out above the upper one, no value of $R$ meets the specification.

WORST-CASE ZENER DISSIPATION

P_{Z, m a x} = V_{Z} (\frac{V _{S, m a x} - V _{Z}}{R} - I_{L, m i n})

Occurs at maximum input with minimum load (usually no load, $I_{L, m i n} = 0$ ).

LINE REGULATION, OUTPUT RESISTANCE AND LOAD REGULATION

\frac{Δ V _{o}}{Δ V _{S}} = \frac{r _{z} ∥ R _{L}}{R + r _{z} ∥ R _{L}}, R_{o} = R ∥ r_{z}, Load reg. = \frac{V _{N L} - V _{F L}}{V _{F L}} \times 100%

Small-change results from the $V_{Z 0} + r_{z} I_{Z}$ model. A change in load current shifts the output by $Δ V_{o} = - R_{o} Δ I_{L}$ . Line regulation is also quoted as a percentage or in mV/V. With $r_{z} = 0$ both regulations are perfect.

WORKED EXAMPLE

A Zener shunt regulator must hold 10 V across a load whose current varies from 0 to 40 mA, while the unregulated input varies from 18 V to 24 V. The Zener ( $V_{Z} = 10$ V, $r_{z} = 0$ ) needs at least 5 mA to regulate and is rated 1 W. Find the permissible range of the series resistor $R$ , and the maximum Zener dissipation with $R = 150 Ω$ .

Solution

$I_{Z, m a x} = P_{Z, m a x} / V_{Z} = 1/10 = 100$ mA.
Upper limit (minimum input, maximum load): $R \leq \frac{18 - 10}{( 5 + 40 ) mA} = \frac{8}{0.045} = 177.8 Ω$ .
Lower limit (maximum input, no load): $R \geq \frac{24 - 10}{( 100 + 0 ) mA} = 140 Ω$ .
With $R = 150 Ω$ the worst case is 24 V with no load: $I_{Z} = 14/150 = 93.3$ mA and $P_{Z} = 10 \times 0.0933 = 0.933$ W, within the 1 W rating.
Check the other extreme: at 18 V and 40 mA, $I_{R} = 8/150 = 53.3$ mA, so $I_{Z} = 13.3$ mA $\geq 5$ mA and the output still regulates.

Answer: $140 Ω \leq R \leq 177.8 Ω$ ; with $R = 150 Ω$ the Zener dissipates at most 0.933 W.

EXAM TIP

The Zener is most stressed with no load at maximum input, so disconnecting the load does not protect it. It is closest to dropping out of regulation with maximum load at minimum input.

EXAM TIP

Always do the breakdown check first. If $R_{L}$ is small enough, the Zener never reaches breakdown and the output is just a voltage divider.

EXAM TIP

Below about 5 V, breakdown is dominated by the Zener (tunnelling) mechanism, which has a negative temperature coefficient. Above about 6 V, avalanche multiplication dominates, with a positive coefficient. Between the two the coefficient is close to zero. Diodes of either kind are called Zener diodes.

Types of diodes and their applications

The IN syllabus lists this topic as types of diode and their applications. This section covers the physical effect each device relies on, how it is normally biased, and what it is used for.

Diode	Physics / construction	Normal bias	Key property	Typical applications
pn rectifier diode	pn junction; minority-carrier injection	Forward to conduct, reverse to block	$V_{γ} \approx 0.7$ V (Si); stored charge causes a reverse-recovery time	Rectifiers, clippers, clampers, protection
Zener	Heavily doped pn junction with a sharp, specified breakdown	Reverse, in breakdown	Nearly constant $V_{Z}$ over a wide current range	Shunt regulators, voltage references, limiters
Schottky	Metal–semiconductor junction; majority-carrier device	Forward	Low forward drop (typically about 0.2–0.4 V); negligible reverse recovery; higher leakage	High-frequency and low-voltage rectifiers, switching supplies, fast clamps
LED	pn junction in a direct-bandgap compound semiconductor	Forward	Radiative recombination; photon energy $\approx E_{g}$ ; forward drop above silicon's, rising with photon energy	Indicators, displays, optocouplers, optical-fibre sources
Photodiode (pn or PIN)	Junction exposed to light; photons generate electron–hole pairs in the depletion region	Reverse	Reverse current proportional to incident optical power; fast response	Light sensing, optical receivers, optocouplers
Solar cell	Large-area pn junction	None (photovoltaic)	Delivers power; open-circuit voltage and short-circuit current depend on illumination	Power generation, light-powered sensors
Varactor	pn junction designed for a strongly bias-dependent junction capacitance	Reverse	Junction capacitance falls as reverse bias rises	Electronic tuning, VCOs, frequency modulators, frequency multipliers
Tunnel diode	Both sides degenerately (very heavily) doped; very thin junction	Small forward bias	Quantum tunnelling gives negative differential resistance between the peak and valley points	Microwave oscillators and amplifiers, very fast switching
PIN diode	Wide intrinsic layer between p and n regions	Forward (RF resistance set by dc current) or reverse (low capacitance)	Acts as a current-controlled resistor at RF	RF switches and attenuators, fast photodetectors

LED EMISSION WAVELENGTH

λ = \frac{h c}{E _{g}} \Rightarrow λ (μ m) \approx \frac{1.24}{E _{g} ( eV )}

Photon energy is approximately the bandgap. For example, $E_{g} = 1.42$ eV gives $λ \approx 0.87 μ$ m (infrared). The same relation gives the longest wavelength a photodiode with bandgap $E_{g}$ can detect.

VARACTOR JUNCTION CAPACITANCE AND TUNED FREQUENCY

C_{j} = \frac{C _{j 0}}{( 1 + V _{R} / V _{bi} ) ^{m}}, f_{0} = \frac{1}{2 π L C _{j}}

$V_{R}$ = reverse bias, $V_{bi}$ = built-in potential. $m = 1/2$ for an abrupt junction and $1/3$ for a linearly graded one; hyperabrupt junctions have $m > 1/2$ . Raising $V_{R}$ lowers $C_{j}$ and raises the tuned frequency (when $C_{j}$ is the only tuning capacitance).

PHOTODIODE RESPONSIVITY

R = \frac{I _{ph}}{P _{opt}} = \frac{η _{q} q λ}{h c} \approx \frac{η _{q} λ ( μ m )}{1.24} A/W

$η_{q}$ = quantum efficiency (electrons collected per incident photon). The photocurrent is proportional to optical power and flows in the diode's reverse direction.

EXAM TIP

Bias to remember: an LED is forward-biased. A photodiode is reverse-biased, and its photocurrent adds to the reverse current, linear in light intensity. A solar cell has no bias and works in the fourth quadrant of its I–V characteristic (with forward current and voltage taken as positive), where it delivers power. A varactor is reverse-biased. A Zener is reverse-biased into breakdown. A tunnel diode used as an oscillator or amplifier is forward-biased in its negative-resistance region.

EXAM TIP

Schottky diodes are fast because they conduct by majority carriers. There is no stored minority charge to remove at turn-off, so reverse recovery is negligible. The trade-offs are higher reverse leakage and, typically, a lower reverse voltage rating than comparable pn diodes.

PREVIOUS-YEAR QUESTIONS

25 questions from the EC, EE and IN papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2026 · GATE ECE 2025 · GATE ECE 2024 · GATE ECE 2023 · GATE ECE 2022 · GATE ECE 2020 · GATE ECE 2018 · GATE EE 2026 · GATE EE 2024 · GATE EE 2023 · GATE EE 2022 · GATE EE 2020 · GATE IN 2026 · GATE IN 2024 · GATE IN 2023 · GATE IN 2022 · GATE IN 2020 · GATE IN 2018

GATE 2026 EC Q.65

GATE 2026 · ECQ.65 · 2 marks · NAT

Consider the ideal diodes D1 and D2 as shown in the Figure with cut-in voltage $V_{γ} = 0$ Volt and $v_{i} (t)$ is in Volt.

The maximum voltage (Volt) of the output $v_{o} (t)$ is ____. (rounded off to two decimal places)

$v_{i} (t) = 6 sin (ω t)$

Answer and solution

GATE 2026 EC Q.65: answer and solution

GATE 2026 EE Q.33

GATE 2026 · EEQ.33 · 1 mark · NAT

In the linear regulator circuit shown, the base to emitter voltage $V_{B E}$ of the BJT is 0.6 V. The Zener diode clamps the base voltage to 5.4 V. Ignore the biasing current of the Zener diode and BJT.

The maximum possible efficiency of the regulator circuit is ________ %

(Round off to one decimal place)

(Figure data: $I_{L} = 100 mA$ , $V_{B E} = 0.6 V$ )

GATE 2026 EE question 33: Series-pass (emitter-follower) linear regulator. — Figure from the GATE 2026 EE paper. It is part of the question.

Answer and solution

GATE 2026 EE Q.33: answer and solution

GATE 2026 IN Q.34

GATE 2026 · INQ.34 · 1 mark · NAT

In the circuit below the maximum value of $v_{o u t}$ is ________ V. (rounded off to the nearest integer)

GATE 2026 IN question 34: An AC source 15 cos ω t (sinusoidal source symbol) on the left; — Figure from the GATE 2026 IN paper. It is part of the question.

Answer and solution

GATE 2026 IN Q.34: answer and solution

GATE 2025 EC Q.57

GATE 2025 · ECQ.57 · 2 marks · MSQ

All the diodes in the circuit given below are ideal.

Which of the following plots is/are correct when $V_{I}$ (in Volts) is swept from $- M$ to $M$ ?

GATE 2025 EC question 57: A voltage source V_I with its + terminal at the top and its − terminal at the bottom. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
Figure — plot of $V_{O}$ (vertical axis) against $V_{I}$ (horizontal axis). It is V-shaped: $V_{O} = M$ at $V_{I} = - M$ , it falls linearly to 0 at the origin, and it rises linearly back to $V_{O} = M$ at $V_{I} = M$ . Dashed lines mark the level M above $V_{I} = \pm M$ .
(B)
Figure — plot of $V_{O}$ against $V_{I}$ . It is a straight line through the origin from $(- M, - M)$ to $(M, M)$ . Dashed lines mark $V_{O} = \pm M$ at $V_{I} = \pm M$ .
(C)
Figure — plot of $I_{I}$ against $V_{I}$ . It is V-shaped: $I_{I} = \frac{M}{R}$ at $V_{I} = - M$ , it falls linearly to 0 at the origin, and it rises linearly back to $\frac{M}{R}$ at $V_{I} = M$ .
(D)
Figure — plot of $I_{I}$ against $V_{I}$ . It is a straight line through the origin from $(- M, - \frac{M}{R})$ to $(M, \frac{M}{R})$ . Dashed lines mark $I_{I} = \pm \frac{M}{R}$ at $V_{I} = \pm M$ .

Answer and solution

GATE 2025 EC Q.57: answer and solution

GATE 2025 EC Q.61

GATE 2025 · ECQ.61 · 2 marks · NAT

The diode in the circuit shown below is ideal. The input voltage (in Volts) is given by $V_{I} = 10 sin 100 π t$ , where time $t$ is in seconds.

The time duration (in ms, rounded off to two decimal places) for which the diode is forward biased during one period of the input is ________.

GATE 2025 EC question 61: A single series loop. — Figure from the GATE 2025 EC paper. It is part of the question.

Answer and solution

GATE 2025 EC Q.61: answer and solution

GATE 2024 EC Q.23

GATE 2024 · ECQ.23 · 1 mark · MCQ

In the circuit shown, the $n : 1$ step-down transformer and the diodes are ideal. The diodes have no voltage drop in forward biased condition. If the input voltage (in Volts) is $V_{s} (t) = 10 sin ω t$ and the average value of load voltage $V_{L} (t)$ (in Volts) is $2.5/ π$ , the value of $n$ is ______.

GATE 2024 EC question 23: Center-tapped full-wave rectifier. — Figure from the GATE 2024 EC paper. It is part of the question.

(A)
4
(B)
8
(C)
12
(D)
16

Answer and solution

GATE 2024 EC Q.23: answer and solution

GATE 2024 EC Q.35

GATE 2024 · ECQ.35 · 1 mark · NAT

As shown in the circuit, the initial voltage across the capacitor is 10 V, with the switch being open. The switch is then closed at $t = 0$ . The total energy dissipated in the ideal Zener diode ( $V_{Z} = 5 V$ ) after the switch is closed (in mJ, rounded off to three decimal places) is ________.

GATE 2024 EC question 35: A single series loop. — Figure from the GATE 2024 EC paper. It is part of the question.

Answer and solution

GATE 2024 EC Q.35: answer and solution

GATE 2024 EE Q.60

GATE 2024 · EEQ.60 · 2 marks · NAT

In the given circuit, the diodes are ideal. The current $I$ through the diode $D 1$ in milliamperes is ________ (rounded off to two decimal places).

GATE 2024 EE question 60: Left branch: a +10 V terminal feeds a 1 kΩ resistor down to node A, and a second 1 kΩ resistor runs from node A to ground. — Figure from the GATE 2024 EE paper. It is part of the question.

Answer and solution

GATE 2024 EE Q.60: answer and solution

GATE 2024 IN Q.23

GATE 2024 · INQ.23 · 1 mark · NAT

Consider the circuit shown in the figure.

[Figure]

The CMOS digital logic circuit has infinite input impedance. Assume the opamp is ideal. A 1.8 V Zener diode with a minimum Zener current of 2 mA is used. The corresponding maximum value of resistance $R_{Z}$ is ________ k $Ω$ . (rounded off to one decimal place).

GATE 2024 IN question 23: An op-amp used open-loop as a comparator. — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.23: answer and solution

GATE 2024 IN Q.57

GATE 2024 · INQ.57 · 2 marks · NAT

In the figure shown, the diode current is given by $I_{D} = I_{S} e^{\frac{α V _{D}}{T}}$ . $V_{D}$ is the diode voltage in volts, $T$ is the absolute temperature in Kelvin, $α = 1.16 \times 1 0^{4} K/V$ , and $I_{S} = 1 0^{- 15} A$ is the saturation current. The dc current source, opamp and the resistors are ideal, and are assumed to be temperature independent. The change in the output voltage ( $V_{o u t}$ ) per Kelvin change in temperature is ________ mV (rounded off to one decimal place).

GATE 2024 IN question 57: A 250 nA dc current source hangs from V_DD and drives its current downward into a node (call it A). — Figure from the GATE 2024 IN paper. It is part of the question.

Answer and solution

GATE 2024 IN Q.57: answer and solution

GATE 2023 EC Q.40

GATE 2023 · ECQ.40 · 2 marks · MCQ

In the circuit shown below, $D_{1}$ and $D_{2}$ are silicon diodes with cut-in voltage of 0.7 V. $V_{I N}$ and $V_{O U T}$ are input and output voltages in volts. The transfer characteristic is

GATE 2023 EC question 40: Input terminal V_IN on the left. — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
Figure: V_OUT vs V_IN. V_OUT is flat at 1 for 0.3 ≤ V_IN ≤ 1.7 (dotted verticals drop from the flat section to V_IN = 0.3 and V_IN = 1.7). For V_IN > 1.7 it rises with slope 1. For V_IN < 0.3 it falls with slope 1 and crosses the V_IN axis at a negative V_IN.
(B)
Figure: V_OUT vs V_IN. V_OUT = 0 for −0.7 ≤ V_IN ≤ 0.7 (a dead zone on the V_IN axis). Outside that range it is a line of slope 1: rising for V_IN > 0.7 and falling below zero for V_IN < −0.7.
(C)
Figure: V_OUT vs V_IN. V_OUT is flat at 1 for −1.7 ≤ V_IN ≤ 1.7 (dotted verticals at −1.7 and 1.7). Outside that range it is a line of slope 1: rising for V_IN > 1.7 and falling for V_IN < −1.7.
(D)
Figure: V_OUT vs V_IN. V_OUT = 0 for 0.3 ≤ V_IN ≤ 1.7 (a flat segment on the V_IN axis). For V_IN > 1.7 it rises with slope 1. For V_IN < 0.3 it falls below zero with slope 1.

Answer and solution

GATE 2023 EC Q.40: answer and solution

GATE 2023 EE Q.44

GATE 2023 · EEQ.44 · 2 marks · MSQ

All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true?

GATE 2023 EE question 44: A common bottom rail (ground) joins the negative terminals of three DC voltage sources and the lower contact of a switch. — Figure from the GATE 2023 EE paper. It is part of the question.

(A)
When switch S is ON, both D1 and D2 conducts and D3 is reverse biased
(B)
When switch S is ON, D1 conducts and both D2 and D3 are reverse biased
(C)
When switch S is OFF, D1 is reverse biased and both D2 and D3 conduct
(D)
When switch S is OFF, D1 conducts, D2 is reverse biased and D3 conducts

Answer and solution

GATE 2023 EE Q.44: answer and solution

GATE 2023 IN Q.33

GATE 2023 · INQ.33 · 1 mark · NAT

The diode in the circuit is ideal. The current source $i_{s} (t) = π sin (3000 π t)$ mA. The magnitude of the average current flowing through the resistor R is ______ mA (rounded off to two decimal places).

GATE 2023 IN question 33: Three elements connected in parallel between a top node and a bottom node: (1) on the left, an independent current source… — Figure from the GATE 2023 IN paper. It is part of the question.

Answer and solution

GATE 2023 IN Q.33: answer and solution

GATE 2022 EC Q.57

GATE 2022 · ECQ.57 · 2 marks · NAT

A circuit and the characteristics of the diode (D) in it are shown. The ratio of the minimum to the maximum small signal voltage gain $\frac{\partial V _{o u t}}{\partial V _{in}}$ is ________ (rounded off to two decimal places).

GATE 2022 EC question 57: Circuit: the input source V_in (+ on top, − at the bottom ground rail) feeds a series 2 k Ω resistor to node A. — Figure from the GATE 2022 EC paper. It is part of the question.

Answer and solution

GATE 2022 EC Q.57: answer and solution

GATE 2022 EE Q.25

GATE 2022 · EEQ.25 · 1 mark · MCQ

For the circuit shown below with ideal diodes, the output will be

GATE 2022 EE question 25: A sinusoidal source V_in (drawn as a sine-wave symbol) sits between two input terminals, with + marked on the upper… — Figure from the GATE 2022 EE paper. It is part of the question.

(A)
$V_{o u t} = V_{in}$ for $V_{in} > 0$
(B)
$V_{o u t} = V_{in}$ for $V_{in} < 0$
(C)
$V_{o u t} = - V_{in}$ for $V_{in} > 0$
(D)
$V_{o u t} = - V_{in}$ for $V_{in} < 0$

Answer and solution

GATE 2022 EE Q.25: answer and solution

GATE 2022 IN Q.31

GATE 2022 · INQ.31 · 1 mark · NAT

A Zener diode is used as a 4 V voltage regulator in the circuit shown. Given that the diode requires a minimum current of 4 mA for voltage regulation, the maximum current (in milliamperes) permitted to flow through the load $R_{L}$ is ________ (round off to one decimal place)

GATE 2022 IN question 31: A 16 V DC voltage source on the left, positive terminal at the top. — Figure from the GATE 2022 IN paper. It is part of the question.

Answer and solution

GATE 2022 IN Q.31: answer and solution

GATE 2022 IN Q.36

GATE 2022 · INQ.36 · 2 marks · MCQ

A signal $V_{in} (t)$ shown is applied from $t = 0$ ms to $t = 6$ ms to the circuit shown. Given the initial voltage across the capacitor is 0.3 V, and that the diode is ideal, the open circuit voltage $V_{o u t} (t)$ at $t = 5$ ms is ________

GATE 2022 IN question 36: Left: plot of V_in (V) against t (ms). — Figure from the GATE 2022 IN paper. It is part of the question.

(A)
0.3 V
(B)
0.6 V
(C)
0.7 V
(D)
1.0 V

Answer and solution

GATE 2022 IN Q.36: answer and solution

GATE 2020 EC Q.17

GATE 2020 · ECQ.17 · 1 mark · NAT

In the circuit shown below, all the components are ideal and the input voltage is sinusoidal. The magnitude of the steady-state output $V_{o}$ (rounded off to two decimal places) is ______ V.

GATE 2020 EC question 17: A two-stage diode-capacitor circuit (a half-wave voltage doubler). — Figure from the GATE 2020 EC paper. It is part of the question.

Answer and solution

GATE 2020 EC Q.17: answer and solution

GATE 2020 EC Q.44

GATE 2020 · ECQ.44 · 2 marks · NAT

In the voltage regulator shown below, $V_{I}$ is the unregulated input at 15 V. Assume $V_{B E} = 0.7 V$ and the base current is negligible for both the BJTs. If the regulated output $V_{O}$ is 9 V, the value of $R_{2}$ is ________ $Ω$ .

GATE 2020 EC question 44: Series transistor voltage regulator. — Figure from the GATE 2020 EC paper. It is part of the question.

Answer and solution

GATE 2020 EC Q.44: answer and solution

GATE 2020 EE Q.31

GATE 2020 · EEQ.31 · 2 marks · MCQ

A non-ideal diode is biased with a voltage of $- 0.03 V$ , and a diode current of $I_{1}$ is measured. The thermal voltage is $26 mV$ and the ideality factor for the diode is $15/13$ . The voltage, in V, at which the measured current increases to $1.5 I_{1}$ is closest to:

(A)
$- 0.02$
(B)
$- 0.09$
(C)
$- 1.50$
(D)
$- 4.50$

Answer and solution

GATE 2020 EE Q.31: answer and solution

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GATE 2020 EE Q.31: answer and solution

GATE 2020 IN Q.7

GATE 2020 · INQ.7 · 1 mark · MCQ

If the diodes in the circuit shown are ideal and the breakdown voltage $V_{Z}$ of the Zener diode is 5 V, the power dissipated in the $100 Ω$ resistor (in watts) is ____

GATE 2020 IN question 7: An AC source 10 sin (100 π t) volts has its bottom terminal grounded. — Figure from the GATE 2020 IN paper. It is part of the question.

(A)
0
(B)
1
(C)
25/100
(D)
225/100

Answer and solution

GATE 2020 IN Q.7: answer and solution

GATE 2020 IN Q.51

GATE 2020 · INQ.51 · 2 marks · NAT

Assume the diodes in the circuit shown are ideal. The current $I_{x}$ flowing through the $3 k Ω$ resistor (in mA, rounded off to one decimal place) is ____

GATE 2020 IN question 51: A central node X (left) and a node Y (right) are joined by a 3 kΩ resistor; — Figure from the GATE 2020 IN paper. It is part of the question.

Answer and solution

GATE 2020 IN Q.51: answer and solution

GATE 2018 EC Q.26

GATE 2018 · ECQ.26 · 2 marks · MCQ

The circuit shown in the figure is used to provide regulated voltage (5 V) across the $1 k Ω$ resistor. Assume that the Zener diode has a constant reverse breakdown voltage for a current range, starting from a minimum required Zener current, $I_{Z m i n} = 2 mA$ to its maximum allowable current. The input voltage $V_{I}$ may vary by 5% from its nominal value of 6 V. The resistance of the diode in the breakdown region is negligible.

The value of $R$ and the minimum required power dissipation rating of the diode, respectively, are

GATE 2018 EC question 26: Zener shunt regulator. — Figure from the GATE 2018 EC paper. It is part of the question.

(A)
186 Ω and 10 mW
(B)
100 Ω and 40 mW
(C)
100 Ω and 10 mW
(D)
186 Ω and 40 mW

Answer and solution

GATE 2018 EC Q.26: answer and solution

GATE 2018 EC Q.37

GATE 2018 · ECQ.37 · 2 marks · NAT

A dc current of $26 μ A$ flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, the diode has a junction capacitance of $0.5 nF$ . Its neutral region resistances can be neglected. Assume that the room temperature thermal equivalent voltage is $26 mV$ .

For $ω = 2 \times 1 0^{6} rad/s$ , the amplitude of the small-signal component of diode current (in $μ A$ , correct to one decimal place) is ________.

GATE 2018 EC question 37: A single series loop. — Figure from the GATE 2018 EC paper. It is part of the question.

Answer and solution

GATE 2018 EC Q.37: answer and solution

GATE 2018 IN Q.16

GATE 2018 · INQ.16 · 1 mark · NAT

The diodes given in the circuit are ideal. At $t = 60 ms$ , $V_{pq}$ (in Volts) is ____.

GATE 2018 IN question 16: A sinusoidal source 100 sin (2 π 50t) V on the left, connected between a top rail (call it A) and a bottom rail (call it B); — Figure from the GATE 2018 IN paper. It is part of the question.

Answer and solution

GATE 2018 IN Q.16: answer and solution

PRACTICE

7 questions to test yourself

PRACTICE 11 mark · MCQ

A half-wave rectifier with an ideal diode is fed from $v_{s} = 10 sin (100 π t)$ V. A capacitor $C$ is connected directly across the load $R_{L}$ , with $R_{L} C ≫ 20$ ms. In steady state, the peak inverse voltage across the diode is closest to

(A)
5 V
(B)
10 V
(C)
14.1 V
(D)
20 V

Answer and solution

Answer: (D)

On the positive half-cycle the diode charges $C$ to the peak, $V_{m} = 10$ V. Because $R_{L} C ≫ 20$ ms, the capacitor stays at about 10 V.
At the input's negative peak the anode is at $- 10$ V while the cathode is held at $+ 10$ V.
Reverse voltage $= 10 - (- 10) = 20$ V $= 2 V_{m}$ .

PRACTICE 22 marks · NAT

In a Zener shunt regulator, a 20 V dc source feeds a load $R_{L}$ through a $200 Ω$ series resistor, with a Zener diode connected across $R_{L}$ . In breakdown the Zener holds $V_{Z} = 8$ V (take $r_{z} = 0$ ), and it regulates only while its current is at least 5 mA. The minimum value of $R_{L}$ (in $Ω$ ) for which the output stays regulated is ______ (round off to two decimal places).

Answer and solution

Answer: $145.45$ (accepted range $\pm 0.5$ )

With the Zener in breakdown the output is 8 V, so $I_{R} = (20 - 8) /200 = 60$ mA whatever the load.
The load may take at most $I_{L, m a x} = I_{R} - I_{Z, m i n} = 60 - 5 = 55$ mA.
$R_{L, m i n} = V_{Z} / I_{L, m a x} = 8/0.055 = 145.45 Ω$ .
Check: without the Zener, this load would sit at $20 \times 145.45/345.45 = 8.42$ V $> 8$ V, so the Zener is indeed in breakdown.

PRACTICE 32 marks · MSQ

Consider full-wave centre-tapped and full-wave bridge rectifiers, both with ideal diodes and a resistive load, fed from a sinusoidal supply of frequency $f$ . Which of the following statements is/are correct?

(A)
For the same peak voltage $V_{m}$ across the load, the PIV rating per diode in the bridge is half that in the centre-tapped circuit.
(B)
The ripple factor of the bridge rectifier is about 0.48.
(C)
The transformer utilisation factor of the bridge rectifier is lower than that of the centre-tapped rectifier.
(D)
In both circuits, the fundamental frequency of the output ripple is $2 f$ .

Answer and solution

Answer: (A), (B), (D)

(A) Bridge: each OFF diode sees $V_{m}$ . Centre-tapped: each half-secondary has peak $V_{m}$ , and the OFF diode sees the whole secondary, $2 V_{m}$ . True.
(B) $RF = FF^{2} - 1 = π^{2} /8 - 1 = 0.483$ . True.
(C) TUF is about 0.81 for the bridge and about 0.69 for the centre-tapped circuit (0.57 on the secondary alone), so the bridge's is higher. False.
(D) Both conduct on every half-cycle, so the output repeats every $T /2$ and the ripple fundamental is $2 f$ . True.

PRACTICE 42 marks · MCQ

$v_{i} = 5 sin ω t$ V is applied through a series capacitor $C$ to an output node. A shunt branch from the output node to ground contains a silicon diode in series with a 3 V battery: the diode's cathode is connected to the output node, its anode to the battery's negative terminal, and the battery's positive terminal is grounded. A resistor $R$ across the output satisfies $R C ≫ 2 π / ω$ . Using the constant-drop model with $V_{γ} = 0.7$ V, the steady-state output swings between

(A)
$- 3.7$ V and $+ 6.3$ V
(B)
$- 3.0$ V and $+ 7.0$ V
(C)
$- 6.3$ V and $+ 3.7$ V
(D)
$- 1.3$ V and $+ 8.7$ V

Answer and solution

Answer: (A)

The anode sits at $V_{R} = - 3$ V. The diode is forward-biased when $V_{anode} - V_{cathode} = - 3 - v_{o} \geq 0.7$ , i.e. $v_{o} \leq - 3.7$ V. So the output can never fall below $- 3.7$ V, and the bottom of the waveform is pinned there.
In steady state the input's negative peak ( $- 5$ V) lands on $- 3.7$ V, so $V_{shift} = - 3.7 - (- 5) = + 1.3$ V.
$v_{o} = v_{i} + 1.3$ V, which swings from $- 3.7$ V to $5 + 1.3 = 6.3$ V. Check: the peak-to-peak is 10 V, equal to the input's.
(B) is the ideal-diode answer; (D) adds the clamp magnitude of 3.7 V instead of the 1.3 V shift.

PRACTICE 52 marks · NAT

$v_{i} = 10 sin ω t$ V drives a $1 k Ω$ series resistor that feeds an output node. A load $R_{L} = 1 k Ω$ is connected from the output node to ground. In parallel with the load is a branch in which a diode has its anode at the output node and its cathode at the positive terminal of a 2 V battery whose negative terminal is grounded. Using the constant-drop model with $V_{γ} = 0.7$ V and no forward resistance, the peak current through the diode (in mA) is ______ (round off to one decimal place).

Answer and solution

Answer: $4.6$ (accepted range $\pm 0.1$ )

The diode is ON when $v_{o} - 2 \geq 0.7$ , i.e. $v_{o} \geq 2.7$ V.
With the diode OFF, the resistors form a divider: $v_{o} = v_{i} /2$ . So the diode starts to conduct at $v_{i} = 5.4$ V, not at 2.7 V.
While it is ON, $v_{o} = 2.7$ V and $i_{D} = \frac{v _{i} - 2.7}{1 k Ω} - \frac{2.7}{1 k Ω}$ , which is largest at $v_{i} = 10$ V.
At $v_{i} = 10$ V: current in the series resistor $= 7.3$ mA, load current $= 2.7$ mA, so $i_{D} = 7.3 - 2.7 = 4.6$ mA.

PRACTICE 61 mark · MCQ

Taking $h c = 1.24$ eV·µm, the longest wavelength of light that a silicon photodiode ( $E_{g} = 1.12$ eV) can detect is closest to

(A)
0.65 µm
(B)
0.87 µm
(C)
1.11 µm
(D)
1.55 µm

Answer and solution

Answer: (C)

A photon is absorbed across the gap only if its energy is at least $E_{g}$ , so the cut-off wavelength is $λ_{c} = h c / E_{g}$ .
$λ_{c} = 1.24/1.12 = 1.107 μ$ m $\approx 1.11 μ$ m.
Longer wavelengths, such as 1.55 µm, carry too little energy to be absorbed by silicon.

PRACTICE 71 mark · NAT

A full-wave rectifier with a capacitor-input filter runs from 50 Hz mains and supplies a load drawing an essentially constant 100 mA. Assume the capacitor discharges at this constant current for the whole interval between successive charging peaks, and neglect the conduction interval. For a peak-to-peak ripple of no more than 1 V, the minimum filter capacitance (in $μ$ F) is ______.

Answer and solution

Answer: $1000$ (accepted range $\pm 1$ )

Full-wave: charging peaks occur every $T /2 = 1/ (2 \times 50) = 10$ ms.
Constant-current discharge: $V_{r} = I_{L} Δ t / C$ .
$C \geq I_{L} Δ t / V_{r} = (0.1) (0.01) /1 = 1 0^{- 3}$ F $= 1000 μ$ F.

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