GATE 2023 EC Q.40: solution and answer

GATE 2023 · ECQ.40 · 2 marks · MCQ

In the circuit shown below, $D_{1}$ and $D_{2}$ are silicon diodes with cut-in voltage of 0.7 V. $V_{I N}$ and $V_{O U T}$ are input and output voltages in volts. The transfer characteristic is

GATE 2023 EC question 40: Input terminal V_IN on the left. — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
Figure: V_OUT vs V_IN. V_OUT is flat at 1 for 0.3 ≤ V_IN ≤ 1.7 (dotted verticals drop from the flat section to V_IN = 0.3 and V_IN = 1.7). For V_IN > 1.7 it rises with slope 1. For V_IN < 0.3 it falls with slope 1 and crosses the V_IN axis at a negative V_IN.
(B)
Figure: V_OUT vs V_IN. V_OUT = 0 for −0.7 ≤ V_IN ≤ 0.7 (a dead zone on the V_IN axis). Outside that range it is a line of slope 1: rising for V_IN > 0.7 and falling below zero for V_IN < −0.7.
(C)
Figure: V_OUT vs V_IN. V_OUT is flat at 1 for −1.7 ≤ V_IN ≤ 1.7 (dotted verticals at −1.7 and 1.7). Outside that range it is a line of slope 1: rising for V_IN > 1.7 and falling for V_IN < −1.7.
(D)
Figure: V_OUT vs V_IN. V_OUT = 0 for 0.3 ≤ V_IN ≤ 1.7 (a flat segment on the V_IN axis). For V_IN > 1.7 it rises with slope 1. For V_IN < 0.3 it falls below zero with slope 1.

Answer and solution

ANSWER

The transfer characteristic is option (A). $V_{O U T}$ stays at $1 V$ for $0.3 \leq V_{I N} \leq 1.7 V$ , follows $V_{I N} - 0.7$ above $1.7 V$ ( $D_{1}$ on) and $V_{I N} + 0.7$ below $0.3 V$ ( $D_{2}$ on).

Official answer: ASource: Official answer key, GATE 2023 EC (IIT Kanpur)

Model and assumptions: $V_{I N}$ is driven by an ideal voltage source. Each diode uses the constant-voltage-drop model: it is off until its forward voltage reaches the cut-in value of $0.7 V$ , and after that it holds a constant $0.7 V$ drop with no series resistance. The output is open-circuited, so any current through the diodes must also flow in the $1 k Ω$ resistor.
Both diodes off: no current flows in the $1 k Ω$ resistor, so there is no drop across it and $V_{O U T} = 1 V$ (the source voltage).
$D_{1}$ (anode at $V_{I N}$ , cathode at $V_{O U T}$ ) turns on when $V_{I N} - V_{O U T} \geq 0.7$ . With $V_{O U T} = 1$ this means $V_{I N} \geq 1.7 V$ . While it conducts, KVL across $D_{1}$ gives $V_{O U T} = V_{I N} - 0.7$ , a line of slope 1. Consistency check: the current from $V_{O U T}$ down through the resistor is $\frac{V _{O U T} - 1}{1 k Ω} = \frac{V _{I N} - 1.7}{1 k Ω} \geq 0$ , which is forward current in $D_{1}$ , as required.
$D_{2}$ (anode at $V_{O U T}$ , cathode at $V_{I N}$ ) turns on when $V_{O U T} - V_{I N} \geq 0.7$ . With $V_{O U T} = 1$ this means $V_{I N} \leq 0.3 V$ . While it conducts, $V_{O U T} = V_{I N} + 0.7$ , again a line of slope 1. Consistency check: the current from the source up through the resistor into $D_{2}$ is $\frac{1 - V _{O U T}}{1 k Ω} = \frac{0.3 - V _{I N}}{1 k Ω} \geq 0$ , which is forward current in $D_{2}$ .
The two diodes are antiparallel, so they never conduct at the same time. The complete characteristic is $V_{O U T} = ⎩ ⎨ ⎧ V_{I N} + 0.7, 1, V_{I N} - 0.7, V_{I N} \leq 0.3 0.3 \leq V_{I N} \leq 1.7 V_{I N} \geq 1.7$
Check: the pieces meet at the breakpoints ( $0.3 + 0.7 = 1$ and $1.7 - 0.7 = 1$ ), so the curve is continuous. At $V_{I N} = 0$ , $V_{O U T} = 0.7$ , so the lower line crosses the $V_{I N}$ axis at $V_{I N} = - 0.7$ , to the left of the origin. This is option (A): flat at $V_{O U T} = 1$ between $V_{I N} = 0.3$ and $V_{I N} = 1.7$ , with slope 1 on both sides.

KEY IDEA

With both diodes off, no current flows in the resistor, so the output sits at the $1 V$ source voltage, not at $0 V$ . Each diode switches on once $V_{I N}$ is $0.7 V$ away from that $1 V$ level: $D_{1}$ at $V_{I N} = 1.7 V$ and $D_{2}$ at $V_{I N} = 0.3 V$ . The result is a flat segment centred on $1 V$ , with the output following the input at unit slope on either side.

WATCH OUT FOR

Measuring the diode thresholds from $0 V$ instead of from the $1 V$ bias. That gives a dead zone of $\pm 0.7 V$ around the origin (option B) or a flat region at $\pm 1.7 V$ (option C). The other trap is taking $V_{O U T} = 0$ while both diodes are off (option D). With no current in the $1 k Ω$ resistor, the output equals the source voltage, $1 V$ .

From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 25 Diode circuits questions, with notes

GATE 2023 EC Q.40: solution and answer

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