A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ____
GATE 2024 CS2 Q.57: solution and answer
Answer and solution
ANSWER
The maximum number of unique opcodes possible for every addressing mode is 32.
Official answer: 32Source: Official answer key, GATE 2024 CS2 (IISc Bengaluru)
Total instruction length is fixed at 32 bits, shared among the opcode field, addressing-mode field, two register-operand fields, and a 16-bit scalar (immediate) field.
16 general purpose registers require bits to encode each register operand; with two register-operand fields this uses bits.
The scalar (immediate) field is given directly as 16 bits.
Bits used so far (both register fields plus the scalar field) bits.
Bits remaining for the opcode field and the addressing-mode field together bits.
8 addressing modes require bits for the addressing-mode field.
Bits left over for the opcode field bits.
Maximum number of unique opcodes possible for every addressing mode .
KEY IDEA
Total instruction width is fixed at 32 bits; every field that is spelled out numerically (register fields, scalar field, addressing-mode field) eats into that budget, and whatever bits remain form the opcode field, whose size determines the count of distinct opcodes as .
WATCH OUT FOR
Forgetting to subtract the addressing-mode field bits before computing the opcode field width, i.e. taking opcode field = 32 − 24 = 8 bits directly (giving 2^8 = 256) instead of first removing the 3 bits needed to encode 8 addressing modes.
From the GATE 2024 CS2 paper. Every question of this paper · Download the full paper · All 11 Instructions & addressing questions, with notes
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