GATE 2025 CS2 Q.28: solution and answer

Official answer: DSource: Official answer key, GATE 2025 CS2 (IIT Roorkee)

1. ISA (Instruction Set Architecture) is the abstract interface between hardware and software that is visible to the programmer/compiler: the instruction set, the addressing modes, and the architecturally visible register set (how many registers exist and how they are named/encoded).

2. Cache memory size (A) and the number of cache levels (C) are microarchitectural implementation choices, not part of the ISA — the ISA does not expose or specify cache organization at all, and two processors implementing the identical ISA (e.g., different processors in the x86 family) can have completely different cache hierarchies.

3. Clock frequency (B) is a physical/implementation parameter of a specific chip, not part of the ISA — different speed grades of the same processor, all implementing the same ISA, run at different clock frequencies.

4. The total number of (architectural) registers (D) is fixed by the ISA specification itself, since machine instructions must reference these registers by a fixed-width encoding/name defined in the ISA (e.g., x86-64 defines 16 general-purpose registers, MIPS defines 32) — this is a software-visible property, unlike microarchitectural resources such as physical register files or reorder buffers.

5. Hence only option D is part of the Instruction Set Architecture; A, B, and C are microarchitecture/implementation details.