GATE 2022 EC Q.28: solution and answer

GATE 2022 · ECQ.28 · 1 mark · MSQ

Select the correct statement(s) regarding CMOS implementation of NOT gates.

(A)
Noise Margin High ( $N M_{H}$ ) is always equal to the Noise Margin Low ( $N M_{L}$ ), irrespective of the sizing of transistors.
(B)
Dynamic power consumption during switching is zero.
(C)
For a logical high input under steady state, the $n$ MOSFET is in the linear regime of operation.
(D)
Mobility of electrons never influences the switching speed of the NOT gate.

See the question in the paper

Answer and solution

ANSWER

Only (C) is correct: with a logic-high input in steady state, the nMOSFET is ON with $V_{D S} = 0$ , so it is in the linear (triode) region.

Official answer: CSource: Official answer key, GATE 2022 EC (IIT Kharagpur)

(A) Noise margins depend on sizing. By definition $N M_{H} = V_{O H} - V_{I H}$ and $N M_{L} = V_{I L} - V_{O L}$ . The switching threshold $V_{M}$ of a CMOS inverter is set by the ratio $\frac{β _{n}}{β _{p}} = \frac{μ _{n} ( W / L ) _{n}}{μ _{p} ( W / L ) _{p}}$ . Only a symmetric inverter ( $β_{n} = β_{p}$ , $V_{T n} = ∣ V_{T p} ∣$ ) has $V_{M} = V_{D D} /2$ and $N M_{H} = N M_{L}$ . Change the sizing and $V_{M}$ shifts, so one margin grows and the other shrinks. The word "always" makes (A) false.
(B) Dynamic power is not zero. Every time the output switches, the load capacitance is charged through the pMOS and discharged through the nMOS: $P_{d y n} = α C_{L} V_{D D}^{2} f$ There is also a short-circuit current while both transistors conduct briefly during the transition. Only the static power is ideally zero, so (B) is false.
(C) Input HIGH, steady state. With $V_{in} = V_{D D}$ : $V_{S Gp} = V_{D D} - V_{D D} = 0 < ∣ V_{T p} ∣$ , so the pMOS is OFF. For the nMOS, $V_{GS n} = V_{D D} > V_{T n}$ , so it is ON. With the pMOS off there is no path to supply current, so in steady state the output settles at $V_{o u t} = 0$ , giving $V_{D S n} = 0$ .
Check the region: $V_{D S n} = 0 < V_{GS n} - V_{T n} = V_{D D} - V_{T n}$ , so the nMOSFET is in the linear (triode) region, acting as a small ON-resistance that holds the output at ground. (C) is true.
(D) Electron mobility sets the pull-down speed. The nMOS drain current is $I_{D n} \propto μ_{n} C_{o x} (W / L)_{n}$ , and the high-to-low propagation delay is $t_{p H L} \approx \frac{C _{L} Δ V}{I _{D n, avg}}$ . A larger $μ_{n}$ gives a faster discharge, so electron mobility does affect switching speed. (This is also why the pMOS is usually made about 2 to 3 times wider: $μ_{p} < μ_{n}$ .) (D) is false.
Only statement (C) is correct.

KEY IDEA

A CMOS inverter draws ideally zero static current, but it still uses dynamic power $α C_{L} V_{D D}^{2} f$ whenever it switches. The ON transistor passes no current in steady state, so its $V_{D S}$ is zero and it sits in the linear (triode) region, not saturation. Noise margins and switching speed both depend on $μ_{n} (W / L)_{n}$ versus $μ_{p} (W / L)_{p}$ . That is why sizing matters, and why electron mobility affects the pull-down delay.

WATCH OUT FOR

Students often mark (B) because they mix up static power (ideally zero) with dynamic switching power (never zero). Another trap is to think the ON nMOS is in saturation because $V_{GS}$ is large. Saturation needs $V_{D S} \geq V_{GS} - V_{T n}$ , and here $V_{D S} = 0$ . Some also mark (A) because they remember the symmetric-inverter case, but the word "always" together with "irrespective of sizing" makes it false.

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GATE 2022 EC Q.28: solution and answer

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