GATE 2026 EE Q.46: solution and answer

GATE 2026 · EEQ.46 · 2 marks · MCQ

The MOSFET switches shown in the circuit are ideal.

[Figure]

Which of the following is the correct option for Boolean logical expression of the output (OUT), and the maximum possible power (P) consumed by the circuit?

GATE 2026 EE question 46: A 5 V supply feeds two resistive-load branches. — Figure from the GATE 2026 EE paper. It is part of the question.

(A)
$OUT = \overline{A B + \overline{C}}$ , $P = 5 mW$
(B)
$OUT = \overline{(A + B) \overline{C}}$ , $P = 5 mW$
(C)
$OUT = \overline{A B \overline{C}} + \overline{C}$ , $P = 7.5 mW$
(D)
$OUT = \overline{A B} C$ , $P = 7.5 mW$

Answer and solution

ANSWER

The answer is (D): $OUT = \overline{A B} C$ and $P_{ma x} = 7.5 mW$ , reached at $A = B = C = 1$ .

Official answer: DSource: Official answer key, GATE 2026 EE (IIT Guwahati)

Right branch: a resistive-load NMOS inverter. When $C = 1$ , $M_{C}$ turns on and pulls node $X$ to 0. When $C = 0$ , $M_{C}$ is off. No current then flows through the 10 kΩ resistor, because a MOSFET gate draws none, so $X = 5 V$ . Hence $X = \overline{C}$ (an overbar means complement throughout).
Left branch: a pull-down network under a 5 kΩ load. Switches in series give AND, and switches in parallel give OR. OUT is pulled low when both $M_{A}$ and $M_{B}$ conduct ( $A B = 1$ ), or when $M_{X}$ conducts ( $X = \overline{C} = 1$ ). Otherwise no current flows and the 5 kΩ resistor pulls OUT high.
So $OUT = \overline{A B + X} = \overline{A B + \overline{C}}$
De Morgan: $\overline{A B + \overline{C}} = \overline{A B} \cdot \overline{\overline{C}} = \overline{A B} C$ . This is exactly the expression in (A) and in (D), so the power figure has to decide between them. (C) reduces to $\overline{A} + \overline{B} + C + \overline{C} = 1$ , a constant, so it is wrong. (B) fails at $A = B = C = 0$ : the circuit gives $OUT = \overline{0 \cdot 0} \cdot 0 = 0$ (here $M_{X}$ is on), but (B) gives $\overline{(0 + 0) \cdot 1} = 1$ .
Power in each branch, with ideal switches ( $R_{o n} = 0$ ): a branch draws $P = V^{2} / R$ when its pull-down path conducts, and nothing otherwise. The right branch draws $\frac{( 5 V ) ^{2}}{10 k Ω} = 2.5 mW$ , only when $C = 1$ . The left branch draws $\frac{( 5 V ) ^{2}}{5 k Ω} = 5 mW$ whenever OUT is pulled low, whether through one path or both, because the 5 kΩ resistor alone sets the current.
Which inputs maximise P? If $C = 0$ , then $M_{X}$ is on: the left branch takes 5 mW and the right branch takes 0, a total of 5 mW. If $C = 1$ , then $M_{X}$ is off; with $A = B = 1$ the series pair conducts, so the left branch takes 5 mW and the right branch takes 2.5 mW.
$P_{ma x} = 5 + 2.5 = 7.5 mW (A = B = C = 1)$
$OUT = \overline{A B} C$ and $P = 7.5 mW$ . That rules out (A), which has the right expression but 5 mW, and the answer is option (D).

KEY IDEA

Treat each resistive-load NMOS stage as a pull-down network: series switches give AND, parallel switches give OR, and the output is the complement of that. The right stage makes $X = \overline{C}$ , which drives $M_{X}$ in parallel with the $A$ – $B$ series pair, so $OUT = \overline{A B + \overline{C}} = \overline{A B} C$ . With ideal switches, a branch dissipates $V^{2} / R$ only while its pull-down path conducts. Both branches can conduct at once only when $C = 1$ and $A B = 1$ , which gives $5 + 2.5 = 7.5 mW$ .

WATCH OUT FOR

The usual slip is to stop once the Boolean expression is found. Option (A) is the same expression as (D), written before applying De Morgan, so you can only separate them by working out the power. The other trap is the power itself: taking the $C = 0$ case, where $M_{X}$ is on, gives only 5 mW, because the right branch is then off. The maximum needs $C = 1$ , which turns the right branch on and $M_{X}$ off, together with $A = B = 1$ so that the left branch still conducts through the series pair.

From the GATE 2026 EE paper. Every question of this paper · Download the full paper · All 7 Logic families questions, with notes

GATE 2026 EE Q.46: solution and answer

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