GATE 2025 EC Q.45: solution and answer

GATE 2025 · ECQ.45 · 2 marks · MCQ

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '0' and $P 1$ is set to logic '1' at all times. The timing diagram of the inputs $S E L$ and $S$ are also shown below.

The sequence of output $Y$ from time $T_{0}$ to $T_{3}$ is ________.

GATE 2025 EC question 45: Circuit: a 2:1 MUX (MUX1) has input 1 = S, input 0 = P0 and select line SEL. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
1011
(B)
0100
(C)
0010
(D)
1101

Answer and solution

ANSWER

The output sequence from $T_{0}$ to $T_{3}$ is $Y = 1011$ , option (A).

Official answer: ASource: Official answer key, GATE 2025 EC (IIT Roorkee)

Read the circuit. A 2:1 MUX passes input 1 when its select line is 1 and input 0 when it is 0. With $P 0 = 0$ and $P 1 = 1$ :
$D_{1} = {S, P 0 = 0, S E L = 1 S E L = 0 = S E L \cdot S, D_{2} = {Q_{1}, P 1 = 1, S E L = 1 S E L = 0$
Find the output. The XOR takes the complemented outputs $\overline{Q_{1}}$ and $\overline{Q_{2}}$ (overline means complement). Complementing both inputs of an XOR does not change its output, because $\overline{A} \oplus \overline{B} = A \oplus B$ . So $Y = Q_{1} \oplus Q_{2}$ .
Find where the flip-flops change. The dashed lines $T_{0}$ to $T_{3}$ sit on the falling edges of CLK. The flip-flops change only on rising edges, and exactly one rising edge comes just before each $T_{k}$ . So $Y (T_{k})$ is set by the state loaded at the rising edge before $T_{k}$ . SEL and S change only between a falling edge and the next rising edge, so each has one clear value at every rising edge. Both flip-flops sample at the same edge. So $D_{2}$ sees the value $Q_{1}$ held just before the edge, not the value FF1 is about to load (D flip-flop rule: $Q^{+} = D$ ).
Rising edge before $T_{0}$ : $S E L = 0$ and $S = 0$ , so $D_{1} = 0$ and $D_{2} = P 1 = 1$ . Then $Q_{1} Q_{2} = 01$ and $Y (T_{0}) = 0 \oplus 1 = 1$ . No initial state is needed, because with $S E L = 0$ neither D input depends on the earlier state.
Rising edge before $T_{1}$ : $S E L = 1$ and $S = 0$ , so $D_{1} = S = 0$ and $D_{2} = Q_{1} = 0$ . Then $Q_{1} Q_{2} = 00$ and $Y (T_{1}) = 0 \oplus 0 = 0$ .
Rising edge before $T_{2}$ : $S E L = 1$ and $S = 1$ , so $D_{1} = 1$ and $D_{2} = Q_{1} = 0$ (the old $Q_{1}$ ). Then $Q_{1} Q_{2} = 10$ and $Y (T_{2}) = 1 \oplus 0 = 1$ .
Rising edge before $T_{3}$ : SEL has already gone back to 0, while $S = 1$ . So $D_{1} = P 0 = 0$ and $D_{2} = P 1 = 1$ . Then $Q_{1} Q_{2} = 01$ and $Y (T_{3}) = 0 \oplus 1 = 1$ .
Result. From $T_{0}$ to $T_{3}$ , $Y = 1, 0, 1, 1$ , so the sequence is 1011, which is option (A).

KEY IDEA

The XOR is fed by both complemented outputs, so $Y = \overline{Q_{1}} \oplus \overline{Q_{2}} = Q_{1} \oplus Q_{2}$ . At each rising edge, read SEL and S. When $S E L = 1$ the two flip-flops act as a 2-bit shift register ( $Q_{1} \leftarrow S$ , $Q_{2} \leftarrow$ old $Q_{1}$ ). When $S E L = 0$ they load the constants $Q_{1} Q_{2} = 01$ , whatever their earlier state. Each $T_{k}$ is a falling edge, so it shows the state loaded at the rising edge just before it.

WATCH OUT FOR

One mistake is feeding FF1's new value into FF2 in the same clock edge, as if the flip-flops rippled. At the third edge this gives $Q_{2} = 1$ and $Y (T_{2}) = 0$ , so the sequence becomes 1001, which is not an option. The other is reading SEL at the dashed line $T_{2}$ , where it is still 1, instead of at the next rising edge, where it is already 0. That gives $Q_{1} Q_{2} = 11$ at $T_{3}$ and the sequence 1010. Taking the XOR inputs as $Q$ instead of $\overline{Q}$ does not change the answer, because complementing both inputs leaves the XOR unchanged.

From the GATE 2025 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2025 EC Q.45: solution and answer

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