GATE 2025 EC Q.43: solution and answer

GATE 2025 · ECQ.43 · 2 marks · MCQ

The identical MOSFETs M $_{1}$ and M $_{2}$ in the circuit given below are ideal and biased in the saturation region. M $_{1}$ and M $_{2}$ have a transconductance $g_{m}$ of 5 mS.

The input signals (in Volts) are:

$V_{1} = 2.5 + 0.01 sin ω t$
$V_{2} = 2.5 - 0.01 sin ω t$

The output signal $V_{3}$ (in Volts) is ________.

GATE 2025 EC question 43: NMOS differential pair. — Figure from the GATE 2025 EC paper. It is part of the question.

(A)
$3 + 0.05 sin ω t$
(B)
$3 - 0.1 sin ω t$
(C)
$4 + 0.1 sin ω t$
(D)
$4 - 0.05 sin ω t$

Answer and solution

ANSWER

$V_{3} = 4 - 0.05 sin ω t$ V, option (D).

Official answer: DSource: Official answer key, GATE 2025 EC (IIT Roorkee)

Assumptions. Both MOSFETs are ideal and in saturation ( $r_{o} \to \infty$ , so channel-length modulation is neglected). The 2 mA tail source is ideal, the devices are matched with $g_{m} = 5 mS$ , and both gates sit at the same DC level of $2.5 V$ .
DC bias (symmetry). The gate voltages are equal and the devices are matched, so the tail current splits equally: $I_{D 1} = I_{D 2} = \frac{2 mA}{2} = 1 mA$ .
DC output (KVL through the drain resistor). $V_{3, DC} = V_{D D} - I_{D 1} R_{D} = 5 - (1 mA) (1 k Ω) = 4 V$ .
Split the input signals. The differential part is $v_{d} = v_{1} - v_{2} = 0.02 sin ω t V$ and the common-mode part is $v_{c m} = \frac{v _{1} + v _{2}}{2} = 0$ . The signal input is purely differential.
Common source node is an AC ground. With a purely differential input the common source node does not move (half-circuit concept), so $v_{g s 1} = + \frac{v _{d}}{2} = 0.01 sin ω t V$ and $v_{g s 2} = - 0.01 sin ω t V$ . This is small enough for the small-signal model: the overdrive voltage is $V_{o v} = \frac{2 I _{D}}{g _{m}} = \frac{2 ( 1 mA )}{5 mS} = 0.4 V$ , and $10 mV ≪ 0.4 V$ .
Small-signal drain current ( $i_{d} = g_{m} v_{g s}$ ). $i_{d 1} = g_{m} \frac{v _{d}}{2} = (5 mS) (0.01 sin ω t V) = 0.05 sin ω t mA$ , flowing down into the drain of M $_{1}$ .
AC output (inverting at the drain). A rise in $i_{d 1}$ increases the drop across the 1 kΩ drain resistor, so the drain voltage falls: $v_{3} = - i_{d 1} R_{D} = - (0.05 sin ω t mA) (1 k Ω) = - 0.05 sin ω t V$ . The single-ended gain is $\frac{v _{3}}{v _{d}} = - \frac{g _{m} R _{D}}{2} = - 2.5$ , which gives the same result.
Superpose DC and AC. $V_{3} = 4 - 0.05 sin ω t V$ This is option (D).

KEY IDEA

In a symmetric differential pair driven by a purely differential signal, the tail current splits equally at DC and the common source node acts as an AC ground. Each drain therefore behaves like a common-source stage driven by half the differential input. At drain 1 the output is $V_{D D} - \frac{I _{S S}}{2} R_{D}$ at DC, plus an AC part of $- g_{m} \frac{v _{d}}{2} R_{D}$ .

WATCH OUT FOR

One mistake is to use the full differential input $v_{d} = 0.02 sin ω t$ rather than $v_{d} /2$ at each gate, which gives $0.1 sin ω t$ (options B, C). Another is to drop the inversion at the drain of M $_{1}$ : $V_{1}$ rising makes $V_{3}$ fall. A third is to put the whole 2 mA tail current through one resistor, which gives a DC level of 3 V instead of 4 V.

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GATE 2025 EC Q.43: solution and answer

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