GATE 2024 EC Q.17: solution and answer

GATE 2024 · ECQ.17 · 1 mark · MCQ

In the circuit below, assume that the long channel NMOS transistor is biased in saturation. The small signal trans-conductance of the transistor is $g_{m}$ . Neglect body effect, channel length modulation and intrinsic device capacitances. The small signal input impedance $Z_{in} (j ω)$ is ________.

GATE 2024 EC question 17: An NMOS transistor. — Figure from the GATE 2024 EC paper. It is part of the question.

(A)
$\frac{- g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$
(B)
$\frac{g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$
(C)
$\frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$
(D)
$\frac{- g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1} + j ω C _{L}}$

Answer and solution

ANSWER

$Z_{in} (j ω) = \frac{- g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$ , option (A).

Official answer: ASource: Official answer key, GATE 2024 EC (IISc Bengaluru)

Small-signal model. The drain is tied to ground, so it is at AC ground. In saturation the MOSFET is a voltage-controlled current source $g_{m} v_{g s}$ that carries current from drain to source. As the question says, take $r_{o} \to \infty$ (no channel-length modulation), ignore body effect and leave out $C_{g s}$ and $C_{g d}$ . Apply a test voltage $V_{x}$ at the gate and let $I_{x}$ be the current it drives into the gate node. Call the source-node voltage $V_{s}$ .
Current through $C_{1}$ . The gate draws no current, so all of $I_{x}$ flows through $C_{1}$ from the gate to the source node. Since $C_{1}$ sits directly between gate and source, the voltage across it is $V_{g s}$ : $V_{g s} = \frac{I _{x}}{j ω C _{1}}$
KCL at the source node. Two currents flow in: $I_{x}$ through $C_{1}$ and $g_{m} V_{g s}$ from the transistor (drain to source). The only path out is $C_{L}$ to ground: $I_{x} + g_{m} V_{g s} = j ω C_{L} V_{s} \Rightarrow V_{s} = \frac{I _{x}}{j ω C _{L}} + \frac{g _{m} I _{x}}{( j ω ) ^{2} C _{1} C _{L}}$
KVL from gate to ground. $V_{x} = V_{g s} + V_{s}$ , so $Z_{in} = \frac{V _{x}}{I _{x}} = \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}} + \frac{g _{m}}{( j ω ) ^{2} C _{1} C _{L}}$
Simplify. Since $(j ω)^{2} = - ω^{2}$ : $Z_{in} (j ω) = \frac{- g _{m}}{C _{1} C _{L} ω ^{2}} + \frac{1}{j ω C _{1}} + \frac{1}{j ω C _{L}}$ This is option (A). The capacitors $C_{1}$ and $C_{L}$ appear in series, and the transistor adds a negative real part $- g_{m} / (ω^{2} C_{1} C_{L})$ . That frequency-dependent negative resistance is what sustains oscillation in a Colpitts oscillator.

KEY IDEA

Drive the gate with a test source. With no gate current, $I_{x}$ flows entirely through $C_{1}$ , so $v_{g s} = I_{x} / (j ω C_{1})$ . The dependent current $g_{m} v_{g s}$ joins $I_{x}$ in charging $C_{L}$ . The result is the two capacitors in series plus a term $g_{m} / ((j ω)^{2} C_{1} C_{L})$ , which is a negative real resistance. This is the standard negative-resistance cell at the heart of the Colpitts oscillator.

WATCH OUT FOR

There are three common slips. (1) Treating $(j ω)^{2}$ as $+ ω^{2}$ , which flips the sign and gives option (B). (2) Leaving out the $g_{m} v_{g s}$ current in the KCL at the source, which leaves only the series capacitors, option (C). (3) Combining $C_{1}$ and $C_{L}$ as if they were in parallel, which gives option (D). They are in series here: the same current $I_{x}$ flows through $C_{1}$ , and the voltages across $C_{1}$ and $C_{L}$ add up to $V_{x}$ .

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GATE 2024 EC Q.17: solution and answer

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