GATE 2025 EE Q.38: solution and answer

GATE 2025 · EEQ.38 · 2 marks · MCQ

In the circuit, $I_{D C}$ is an ideal current source. The transistors $M_{1}$ and $M_{2}$ are assumed to be biased in saturation, wherein $V_{in}$ is the input signal and $V_{D C}$ is fixed DC voltage. Both transistors have a small signal resistance of $r_{d s}$ and trans-conductance of $g_{m}$ . The small signal output impedance of this circuit is

GATE 2025 EE question 38: NMOS cascode stage. — Figure from the GATE 2025 EE paper. It is part of the question.

(A)
$2 r_{d s}$
(B)
$\frac{1}{g _{m}} + r_{d s}$
(C)
$g_{m} r_{d s}^{2} + 2 r_{d s}$
(D)
infinity

Answer and solution

ANSWER

The small-signal output impedance is $g_{m} r_{d s}^{2} + 2 r_{d s}$ , option (C).

Official answer: CSource: Official answer key, GATE 2025 EE (IIT Roorkee)

Set up the small-signal circuit. To find the output impedance, set the input to zero. $V_{in}$ becomes AC ground. $V_{D C}$ is a fixed DC voltage, so the gate of $M_{2}$ is also at AC ground. An ideal current source $I_{D C}$ has infinite small-signal resistance, so it is an open circuit. What remains is the cascode $M_{2}$ – $M_{1}$ , seen from the drain of $M_{2}$ .
Model. Both MOSFETs are in saturation. Each is modelled as a controlled source $g_{m} v_{g s}$ from drain to source, with $r_{d s}$ in parallel with it. Body effect is neglected, because the question gives only $g_{m}$ and $r_{d s}$ .
Apply a test source. Drive a test voltage $v_{x}$ into the $V_{o u t}$ node. The current $i_{x}$ it delivers flows down through $M_{2}$ and then through $M_{1}$ to ground, since the source of $M_{2}$ connects only to the drain of $M_{1}$ .
Lower device $M_{1}$ . Its gate and source are both at AC ground, so $v_{g s 1} = 0$ . Its controlled source is therefore dead and $M_{1}$ acts as a plain resistor $r_{d s}$ . The whole of $i_{x}$ flows through it, so the voltage at the source of $M_{2}$ is $v_{s} = i_{x} r_{d s}$ .
Upper device $M_{2}$ . With its gate at AC ground, $v_{g s 2} = 0 - v_{s} = - i_{x} r_{d s}$ . KCL at the drain of $M_{2}$ : the current entering the drain splits between the controlled source and $r_{d s}$ , so $i_{x} = g_{m} v_{g s 2} + \frac{v _{x} - v _{s}}{r _{d s}} = - g_{m} r_{d s} i_{x} + \frac{v _{x} - i _{x} r _{d s}}{r _{d s}}$
Solve for $v_{x}$ . Multiply through by $r_{d s}$ and collect terms: $i_{x} r_{d s} = - g_{m} r_{d s}^{2} i_{x} + v_{x} - i_{x} r_{d s}$ $v_{x} = (g_{m} r_{d s}^{2} + 2 r_{d s}) i_{x}$ The resistance looking into the drain of $M_{2}$ is therefore $g_{m} r_{d s}^{2} + 2 r_{d s}$ .
Combine with the current source. The ideal current source (infinite resistance) is in parallel with this at the output node, so $R_{o u t} = \infty ∥ (g_{m} r_{d s}^{2} + 2 r_{d s}) = g_{m} r_{d s}^{2} + 2 r_{d s}$ This is option (C).

KEY IDEA

Looking into the drain of a MOSFET whose source has a resistance $R_{S}$ to ground gives $R = r_{d s} + R_{S} + g_{m} r_{d s} R_{S}$ . In a cascode, $R_{S}$ is the $r_{d s}$ of the lower transistor, so $R = 2 r_{d s} + g_{m} r_{d s}^{2}$ . The ideal current-source load is an open circuit in parallel with this, so it leaves the result unchanged.

WATCH OUT FOR

Choosing (D) because the load is an ideal current source. The infinite resistance is in PARALLEL with the cascode at the output node, not in series, so it drops out and leaves the finite cascode resistance. Choosing (A) means treating $M_{2}$ as nothing more than $r_{d s}$ and missing the $g_{m} r_{d s}^{2}$ boost that comes from its source being degenerated by $M_{1}$ . Choosing (B) means treating $M_{2}$ as a source follower or diode ( $1/ g_{m}$ ), but here the output is taken at its drain.

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GATE 2025 EE Q.38: solution and answer

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