GATE 2023 EC Q.24: solution and answer

GATE 2023 · ECQ.24 · 1 mark · MCQ

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

GATE 2023 EC question 24: Three positive-edge-triggered D flip-flops connected in cascade (a 3-stage serial-in serial-out shift register). — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
1000, 3
(B)
333.33, 1
(C)
2000, 3
(D)
333.33, 3

Answer and solution

ANSWER

Throughput = 1000 Mbits/s and latency = 3 ns, so the answer is option (A).

Official answer: ASource: Official answer key, GATE 2023 EC (IIT Kanpur)

The circuit is a 3-stage shift register, which works as a 3-stage pipeline. All three D flip-flops share one clock, so on every active clock edge each bit moves one stage to the right: $Q_{0} \leftarrow Input$ , $Q_{1} \leftarrow Q_{0}$ , $Q_{2} \leftarrow Q_{1}$ .
Clock period: $T_{c l k} = \frac{1}{f _{c l k}} = \frac{1}{1 GHz} = 1 ns$ .
Throughput is the rate at which bits leave the output once the pipeline is full. On every clock edge a new bit enters at $D_{0}$ and a new bit appears at $Q_{2}$ , so the circuit delivers one bit per clock cycle: throughput $= \frac{1 bit}{1 ns} = 1 0^{9} bits/s = 1000 Mbits/s$ .
Throughput does not depend on the number of stages. The three flip-flops hold three different bits at the same time, so they work in parallel, not one after another.
Latency is the time one particular bit takes to travel from Input to Output. The bit has to be clocked through all three flip-flops, one stage per edge, so it takes 3 clock cycles: latency $= 3 \times T_{c l k} = 3 \times 1 ns = 3 ns$ .
So the throughput is $1000 Mbits/s$ and the latency is $3 ns$ , which is option (A).

KEY IDEA

In a pipeline driven by one clock, throughput is set by the clock alone: one bit per cycle, so $f_{c l k}$ bits/s whatever the number of stages. Latency is set by the depth: $N$ stages take $N$ clock periods. Here that gives $1 bit/ns = 1000 Mbits/s$ and $3 \times 1 ns = 3 ns$ .

WATCH OUT FOR

Dividing the clock rate by the number of stages (1000/3 = 333.33 Mbits/s, options B and D), as if each bit had to clear the whole register before the next could enter. In fact all three stages hold different bits at once, so a bit leaves on every clock. A second mistake is to take the latency as one clock period (1 ns, option B) when a bit has to pass through all three flip-flops.

From the GATE 2023 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2023 EC Q.24: solution and answer

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