GATE 2026 EC Q.49: solution and answer

GATE 2026 · ECQ.49 · 2 marks · MCQ

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.

Which of the following options gives the correct binary representation $(b_{7} b_{6} b_{5} b_{4} b_{3} b_{2} b_{1} b_{0})$ of the content of the shift register immediately after the $5^{th}$ clock transition (positive edge)?

GATE 2026 EC question 49: An 8-bit shift register labelled 'SR (Shift Left)' with cells b7 b6 b5 b4 b3 b2 b1 b0 from left to right. — Figure from the GATE 2026 EC paper. It is part of the question.

(A)
$(00011111)_{2}$
(B)
$(10111111)_{2}$
(C)
$(00111111)_{2}$
(D)
$(11000011)_{2}$

Answer and solution

ANSWER

Immediately after the 5th positive edge the register holds $(b_{7} \dots b_{0}) = (00011111)_{2}$ . The answer is option (A).

Official answer: ASource: Official answer key, GATE 2026 EC (IIT Guwahati)

Read the connections. The serial input of the shift-left register is the XOR output: $b_{0}^{+} = Q \oplus 1 = \overline{Q}$ (overline = complement). The D flip-flop samples the bit being shifted out: $Q^{+} = D = b_{7}$ . On each positive edge, $b_{7} \leftarrow b_{6}, b_{6} \leftarrow b_{5}, \dots, b_{1} \leftarrow b_{0}, b_{0} \leftarrow \overline{Q}$ .
Synchronous update rule. The register and the flip-flop share one clock edge, so every new value is computed from the values present just before that edge. The XOR has no delay, so it simply keeps $\overline{Q}$ at the serial input.
Initial state: $S R = (00000000)_{2}$ and $Q = 0$ , so the serial input is $\overline{Q} = 1$ .
Clock 1: $b_{0} \leftarrow 1$ and $Q \leftarrow b_{7} = 0$ , giving $S R = (00000001)_{2}$ .
Clocks 2 to 4: before each of these edges $b_{7} = 0$ , so $Q$ stays 0 and another 1 enters at $b_{0}$ each time: $(00000011)_{2} \to (00000111)_{2} \to (00001111)_{2}$ .
Clock 5: just before the edge $b_{7} = 0$ and $Q = 0$ , so another 1 enters: $S R = (00011111)_{2}$ .
Why the feedback never acts here. The first 1 enters $b_{0}$ at edge 1 and does not reach $b_{7}$ until edge 8, so $Q$ cannot become 1 before edge 9. The first five edges therefore just shift in five 1s from the right, and the content is $(00011111)_{2}$ : option (A).

KEY IDEA

XOR with a constant 1 is an inverter, so the serial input is $\overline{Q}$ . $Q$ samples $b_{7}$ , which stays 0 until a 1 has travelled all 8 cells, so for the first 8 edges $Q = 0$ and a 1 shifts in at $b_{0}$ on every edge.

WATCH OUT FOR

Taking the serial input as $Q$ instead of $Q \oplus 1 = \overline{Q}$ leaves the register at all zeros, which is not an option. Filling from the $b_{7}$ end, as if it were a shift-right register, gives $(11111000)_{2}$ , also not an option. Counting one edge too many (for example, treating the initial clear as a clock) gives six 1s, $(00111111)_{2}$ , which is the trap option (C).

From the GATE 2026 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2026 EC Q.49: solution and answer

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