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GATE 2020 IN Q.40: solution and answer

GATE 2020 · INQ.40 · 2 marks · NAT

Two T-flip flops are interconnected as shown in the figure. The present state of the flip flops are: A = 1, B = 1. The input x is given as 1, 0, 1 in the next three clock cycles. The decimal equivalent of with A being the MSB and y being the LSB, after the 3rd clock cycle is ____

GATE 2020 IN question 40: Two T flip-flops, A (top) and B (bottom), share a common clock line labelled clk.Tap to open full size
Figure from the GATE 2020 IN paper. It is part of the question.
Figure description

Two T flip-flops, A (top) and B (bottom), share a common clock line labelled clk. Both clock inputs are edge-triggered (triangle, no bubble). Input x feeds one input of a 2-input NAND gate and, through a junction, also goes straight down and across to the T input of flip-flop B (so T_B = x). The second input of the NAND gate comes from output B: a wire leaves the NAND's lower input, runs down, crosses the clock line with no junction, and joins B's output at a junction dot. The NAND output drives T_A (so T_A = (x B)'). Output A and output B are the two inputs of an OR gate whose output is y (y = A + B). No other connections; the flip-flops have only T, clk and a single output (A or B).

Answer and solution

ANSWER

After the third clock, , and , so .

Official answer: 7Source: Official answer key, GATE 2020 IN (IIT Delhi)

  1. Read the circuit (complement written with ): the NAND gate takes and , so ; the wire from the junction goes straight to flip-flop B, so ; the OR gate takes and , so .

  2. T flip-flop rule: . The flip-flop toggles when and holds when . The T inputs are worked out from the present state, before the clock edge.

  3. Clock 1 (, present , ): , so A holds at 1. , so B toggles to 0. New state .

  4. Clock 2 (, present , ): , so A toggles to 0. , so B holds at 0. New state .

  5. Clock 3 (, present , ): , so A toggles to 1. , so B toggles to 1. New state .

  6. Output after the 3rd clock: is a purely combinational function of the new state, so .

  7. .

KEY IDEA

Write down the excitation equations from the gates (, ). Then step through a state table one clock at a time, working each T input out from the present state and that cycle's , and using . The output is combinational, so read it from the state after the 3rd clock.

WATCH OUT FOR

The usual slips: (i) reading the gate as an AND and forgetting the bubble, which gives and a different sequence; (ii) working a cycle's out from the value B will have after the edge instead of its present value (at clock 1, for example, uses , not the new ); (iii) taking from the state before the 3rd clock, or leaving out of the 3-bit word.

From the GATE 2020 IN paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

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