GATE 2018 IN Q.17: solution and answer

GATE 2018 · INQ.17 · 1 mark · NAT

For the 3-bit binary counter shown in the figure, the output increments at every positive transition in the clock (CLK). Assume ideal diodes and the starting state of the counter as 000. If output high is 1 V and output low is 0 V, the current $I$ (in mA) flowing through the 50 $Ω$ resistor during the 5 $^{th}$ clock cycle is (up to one decimal place) ______.

GATE 2018 IN question 17: A block labelled '3-bit binary counter' has a clock input CLK on its lower left, marked with the edge-trigger triangle. — Figure from the GATE 2018 IN paper. It is part of the question.

Answer and solution

ANSWER

During the 5th clock cycle the counter reads $(101)_{2}$ . Both $100 Ω$ branches feed the $50 Ω$ resistor, which sinks into the LOW middle bit, so $I = 1 V / ((100 ∥ 100) + 50) Ω = 10.0 mA$ .

Official answer: 10Source: Official answer key, GATE 2018 IN (IIT Guwahati)

Reading the circuit. Call the counter outputs $Q_{2}$ (MSB), $Q_{1}$ (middle bit, unlabelled in the figure) and $Q_{0}$ (LSB). The MSB and LSB diodes point away from the counter, so each can only push current from a HIGH output through its $100 Ω$ resistor to the junction X. The middle-bit diode points into the counter, so the $50 Ω$ branch carries current from X into the middle bit only when that bit is LOW. Current $I$ therefore flows only when $Q_{1} = 0$ and at least one of $Q_{2}$ or $Q_{0}$ is 1.
Finding the counter state. The counter starts at $(000)_{2}$ and goes up by one on every positive clock edge. Each clock cycle begins with a rising edge, so the edge that starts clock cycle $n$ sets the count to $n$ . During the 5th clock cycle the state is therefore $(101)_{2}$ : $Q_{2} = 1$ , $Q_{1} = 0$ , $Q_{0} = 1$ .
Diode states for 101. The MSB and LSB diodes each have 1 V on the anode side, so both conduct (ideal diodes, 0 V drop). The middle-bit diode has its cathode at 0 V and conducts. The two $100 Ω$ branches are then two 1 V sources in parallel feeding X.
KCL at X: $2 \cdot \frac{1 - V _{X}}{100} = \frac{V _{X} - 0}{50} \Rightarrow \frac{1 - V _{X}}{50} = \frac{V _{X}}{50} \Rightarrow V_{X} = 0.5 V$
Current in the 50 Ω resistor: $I = \frac{V _{X}}{50} = \frac{0.5}{50} A = 10 mA$ Check with an equivalent resistance: $(100 ∥ 100) + 50 = 100 Ω$ , so $I = 1 V /100 Ω = 10 mA$ . The assumed diode states hold: each $100 Ω$ branch carries $(1 - 0.5) /100 = 5 mA$ forward, and the middle diode carries the full $10 mA$ forward. To one decimal place, $I = 10.0 mA$ .
Sanity check against the other states. For 001 and 100 only one diode conducts, so $I = 1/ (100 + 50) A = 6.67 mA$ . For 000, 010, 011, 110 and 111, $I = 0$ : either no output is HIGH, or the middle-bit diode's cathode sits at 1 V and blocks, because X can never rise above 1 V. Only 101 gives the parallel pair, which is why the state during the 5th cycle decides this question.

KEY IDEA

Work out the counter state during the asked-for clock cycle, then use the diode directions to find which branches conduct. The MSB and LSB diodes can only source current from a HIGH output. The middle diode can only sink current into a LOW middle bit. In state 101 two 1 V sources, each behind $100 Ω$ , act in parallel through $50 Ω$ into 0 V.

WATCH OUT FOR

Taking the state during the 5th clock cycle to be $(100)_{2}$ (the count before the 5th edge) instead of $(101)_{2}$ . That leaves only the MSB branch conducting and gives $1/150 A = 6.7 mA$ . A second slip is misreading the middle diode's direction. It points INTO the counter, so current flows only when the middle bit is 0; if you treat it as a source like the other two you get the wrong network.

From the GATE 2018 IN paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2018 IN Q.17: solution and answer

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