GATE 2018 EE Q.36: solution and answer

GATE 2018 · EEQ.36 · 2 marks · MCQ

Which one of the following statements is true about the digital circuit shown in the figure

GATE 2018 EE question 36: Three D flip-flops sit side by side. — Figure from the GATE 2018 EE paper. It is part of the question.

(A)
It can be used for dividing the input frequency by 3.
(B)
It can be used for dividing the input frequency by 5.
(C)
It can be used for dividing the input frequency by 7.
(D)
It cannot be reliably used as a frequency divider due to disjoint internal cycles.

Answer and solution

ANSWER

(B) It can be used for dividing the input frequency by 5.

Official answer: BSource: Official answer key, GATE 2018 EE (IIT Guwahati)

Read the circuit as a 3-bit shift register with NAND feedback. A prime ( $^{'}$ ) means complement. The inputs are $D_{1} = (Q_{2} Q_{3})^{'}$ , $D_{2} = Q_{1}$ and $D_{3} = Q_{2}$ . A D flip-flop's next state equals its D input, so $Q_{1}^{+} = (Q_{2} Q_{3})^{'}$ , $Q_{2}^{+} = Q_{1}$ and $Q_{3}^{+} = Q_{2}$ .
Start from $Q_{1} Q_{2} Q_{3} = 100$ . Here $Q_{2} Q_{3} = 0$ , so $D_{1} = 1$ . The next state is $110$ .
At $110$ , $Q_{2} Q_{3} = 0$ , so the next state is $111$ . At $111$ , $Q_{2} Q_{3} = 1$ , so $D_{1} = 0$ and the next state is $011$ .
At $011$ , $Q_{2} Q_{3} = 1$ , so the next state is $001$ . At $001$ , $Q_{2} Q_{3} = 0$ , so the next state is $100$ , which is where we started. The main cycle is $100 \to 110 \to 111 \to 011 \to 001 \to 100$ and it has 5 states.
Option (D) is about lock-out, so check the three unused states. $000 \to 100$ , which joins the cycle. $010 \to 101$ , because $Q_{3} = 0$ makes $D_{1} = 1$ . $101 \to 110$ , which joins the cycle. None of them forms a separate loop, so there are no disjoint cycles and the counter starts itself from any power-up state.
The output is $f_{O U T} = Q_{3}$ . Around the cycle it reads $0, 0, 1, 1, 1$ and repeats every 5 clock pulses. So $f_{O U T} = f_{I N} /5$ , with a duty cycle of $3/5 = 60%$ .
The circuit is a self-starting mod-5 counter, so it divides the input frequency by 5. The answer is (B).

KEY IDEA

A shift register with feedback is a counter. Its division ratio is the length of the state cycle, which you find by stepping through the next-state equations $Q_{1}^{+} = (Q_{2} Q_{3})^{'}$ , $Q_{2}^{+} = Q_{1}$ , $Q_{3}^{+} = Q_{2}$ . Here the cycle has 5 states. To rule out lock-out, check where every unused state goes. All three unused states here lead into the main cycle, so the counter starts itself and divides by 5.

WATCH OUT FOR

Seeing three flip-flops and assuming divide-by-3 (a ring counter) or divide-by-7/8. Another trap is picking (D) without tracing the unused states. $000$ , $010$ and $101$ all feed into the 5-state cycle, so there is no disjoint loop. A third slip is reading the NAND inputs as $Q_{1}$ and $Q_{3}$ instead of $Q_{2}$ and $Q_{3}$ .

From the GATE 2018 EE paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2018 EE Q.36: solution and answer

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