GATE 2018 EC Q.46: solution and answer

GATE 2018 · ECQ.46 · 2 marks · NAT

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data $D_{in}$ using clock $C K$ . The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of $Δ T / T_{C K} = 0.15$ , where the parameters $Δ T$ and $T_{C K}$ are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.

If the probability of input data bit ( $D_{in}$ ) transition in each clock period is 0.3, the average value (in volts, accurate to two decimal places) of the voltage at node $X$ , is ______.

GATE 2018 EC question 46: Circuit (left): input terminal D_in feeds the D input of a D Flip-Flop; — Figure from the GATE 2018 EC paper. It is part of the question.

Answer and solution

ANSWER

The average voltage at node $X$ is $3.3 \times 0.3 \times 0.85 = 0.8415 \approx 0.84 V$ .

Official answer: 0.82 to 0.86Source: Official answer key, GATE 2018 EC (IIT Guwahati)

When does the flip-flop sample? $D_{in}$ changes $Δ T$ after each rising edge of $C K$ . So at every rising edge the flip-flop captures the bit that has been on $D_{in}$ since just after the previous edge. Call the rising edges $t_{k}$ and call $b_{k}$ the bit that appears on $D_{in}$ at $t_{k} + Δ T$ . Then at edge $t_{k}$ the input still holds $b_{k - 1}$ , and $Q \to b_{k - 1}$ .
Interval $[t_{k}, t_{k} + Δ T]$ , just after the edge: $D_{in}$ has not changed yet, so $D_{in} = b_{k - 1} = Q$ . That makes $X = D_{in} \oplus Q = 0$ in every period.
Interval $[t_{k} + Δ T, t_{k + 1}]$ : $D_{in}$ has moved on to $b_{k}$ , but $Q$ still holds $b_{k - 1}$ until the next edge. So $X = b_{k} \oplus b_{k - 1}$ , which is 1 only if the data bit changed in this period. This interval lasts $T_{C K} - Δ T$ .
Fraction of a period in which $X$ is HIGH, given a transition: $\frac{T _{C K} - Δ T}{T _{C K}} = 1 - 0.15 = 0.85$ . With no transition, $X = 0$ for the whole period.
Average over many periods (expected value): a transition happens in a period with probability $0.3$ , and $X$ is $3.3 V$ when HIGH, so
$\overline{V_{X}} = 3.3 \times 0.3 \times 0.85 = 0.8415 V$
To two decimal places, $\overline{V_{X}} \approx 0.84 V$ .

KEY IDEA

$X = D_{in} \oplus Q$ compares the new data bit with the previous bit held in the flip-flop. $X$ is HIGH only between the moment $D_{in}$ changes ( $Δ T$ after an edge) and the next rising edge, when the flip-flop copies the new bit into $Q$ . That window is $T_{C K} - Δ T$ long and appears only in periods where the data changes. So the average is $V_{H} \times P (transition) \times (1 - Δ T / T_{C K})$ .

WATCH OUT FOR

Taking the HIGH window of $X$ as $Δ T$ instead of $T_{C K} - Δ T$ . That gives $3.3 \times 0.3 \times 0.15 \approx 0.15 V$ . The edge samples the OLD bit, because $D_{in}$ changes only after the edge. So $Q$ lags $D_{in}$ for almost the whole period, not just for $Δ T$ . Other slips are leaving out the transition probability (giving $2.81 V$ ) and multiplying by the clock's 50% duty cycle, which has nothing to do with the output.

From the GATE 2018 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2018 EC Q.46: solution and answer

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