GATE EC

MOS capacitor, MOSFET and scaling

Study notes for the GATE Electronic Devices topic 'MOS capacitor, MOSFET and scaling' (EC syllabus): conventions, oxide capacitance, work-function difference and flat-band voltage; accumulation, depletion, weak and strong inversion; threshold voltage for NMOS and PMOS with body effect and threshold-adjust implant; low- and high-frequency C-V and C_min; the square-law I-V model with channel-length modulation; transconductance, body transconductance and f_T; subthreshold conduction and swing; constant-field vs constant-voltage scaling and short-channel effects. Includes worked examples, a formula sheet and five original GATE-style practice questions.

7 previous-year questions · 7 solved · 5 practice questions

MOS Capacitor: Conventions, Oxide Capacitance and Flat-Band Voltage

Conventions used throughout: an NMOS structure (gate, oxide, p-type Si body of acceptor doping $N_{A}$ ) unless stated otherwise; electron charge $q = 1.6 \times 1 0^{- 19} C$ ; thermal voltage $V_{T} = k T / q = 25.9 mV$ at 300 K; $n_{i} = 1.5 \times 1 0^{10} cm^{- 3}$ for Si at 300 K; $ε_{0} = 8.85 \times 1 0^{- 14} F/cm$ , $ε_{s i} = 11.7 ε_{0}$ , $ε_{o x} = 3.9 ε_{0}$ (SiO $_{2}$ ). Concentrations are in cm $^{- 3}$ . Charges and capacitances are per unit gate area (C/cm $^{2}$ , F/cm $^{2}$ ) unless marked 'per device'. MOSFET voltages are measured from the source, and $V_{S B} \geq 0$ means the source-body junction is reverse-biased. The surface potential $ϕ_{s}$ is the band bending at the Si surface measured from the flat-band condition, taken positive when the bands bend down (towards inversion for a p-type body).

A MOS capacitor is a gate electrode separated from a semiconductor body by a thin insulator. The gate voltage $V_{G}$ (measured with respect to the body) controls the charge at the semiconductor surface, and the same physics sets the threshold voltage of a MOSFET. The flat-band voltage $V_{F B}$ is the gate voltage at which the bands are flat right up to the surface, so there is no band bending and no space charge in the silicon. The surface regimes below are counted from this point.

OXIDE CAPACITANCE PER UNIT AREA

C_{o x} = \frac{ε _{o x}}{t _{o x}}

$ε_{o x} = 3.9 ε_{0}$ for SiO $_{2}$ ; $t_{o x}$ is the oxide thickness. This is the parallel-plate result: it ignores polysilicon-gate depletion and the finite thickness of the inversion layer. Example: $t_{o x} = 10 nm$ gives $C_{o x} = 3.45 \times 1 0^{- 7} F/cm^{2}$ .

BULK FERMI POTENTIAL (P-TYPE BODY)

ϕ_{F} = \frac{k T}{q} ln (\frac{N _{A}}{n _{i}})

Valid for a non-degenerate, fully ionised body with $N_{A} ≫ n_{i}$ ; $ϕ_{F} > 0$ here. For an n-type body (PMOS) the magnitude is $∣ ϕ_{F} ∣ = V_{T} ln (N_{D} / n_{i})$ and $ϕ_{F}$ is negative. Example: $N_{A} = 1 0^{16} cm^{- 3}$ gives $ϕ_{F} = 0.0259 ln (6.67 \times 1 0^{5}) \approx 0.347 V$ .

GATE-BODY WORK-FUNCTION DIFFERENCE (P-TYPE BODY)

ϕ_{m s} = ϕ_{m} - (χ + \frac{E _{g}}{2 q} + ϕ_{F})

$ϕ_{m}$ is the gate work function and $χ$ the electron affinity of Si (about 4.05 V), both in volts. $E_{g} \approx 1.12 eV$ for Si at 300 K, and the intrinsic level is taken at midgap. The bracket is the work function of the p-type body. For an n $^{+}$ polysilicon gate ( $ϕ_{m} \approx χ$ ) this gives $ϕ_{m s} \approx - (\frac{E _{g}}{2 q} + ϕ_{F})$ . For an n-type body, replace $+ ϕ_{F}$ by $- ∣ ϕ_{F} ∣$ .

FLAT-BAND VOLTAGE

V_{F B} = ϕ_{m s} - \frac{Q _{o x}}{C _{o x}}

$Q_{o x}$ is the effective oxide charge per unit area (C/cm $^{2}$ ), treated as a sheet at the oxide-silicon interface. Charge located deeper in the oxide, closer to the gate, shifts $V_{F B}$ less. Positive $Q_{o x}$ makes $V_{F B}$ more negative, and negative $Q_{o x}$ makes it more positive.

Surface Potential: Accumulation, Depletion and Inversion (p-type body, NMOS)

As the gate voltage is raised from below $V_{F B}$ , the surface of a p-type body passes through the regimes below in order. Here $n_{s}$ and $p_{s}$ are the surface electron and hole concentrations.

Regime	Gate bias	Surface potential	Surface condition
Accumulation	$V_{G} < V_{F B}$	$ϕ_{s} < 0$	Holes (majority carriers) pile up at the surface
Flat band	$V_{G} = V_{F B}$	$ϕ_{s} = 0$	No band bending, no space charge in the Si
Depletion	$V_{F B} < V_{G} < V_{T H}$ (lower part)	$0 < ϕ_{s} < ϕ_{F}$	Holes pushed away, ionised acceptors exposed; $p_{s} > n_{s}$
Weak inversion	$V_{F B} < V_{G} < V_{T H}$ (upper part)	$ϕ_{F} < ϕ_{s} < 2 ϕ_{F}$	$n_{s} > p_{s}$ but $n_{s} < N_{A}$ ; inversion charge small compared with depletion charge
Onset of strong inversion	$V_{G} = V_{T H}$	$ϕ_{s} = 2 ϕ_{F}$	$n_{s} = N_{A}$ : surface electron density equals the bulk hole density
Strong inversion	$V_{G} > V_{T H}$	$ϕ_{s} \approx 2 ϕ_{F}$ (rises only by a few $k T / q$ )	Inversion electrons screen the body; depletion width stays at $W_{d m}$

MAXIMUM DEPLETION WIDTH

W_{d m} = \frac{4 ε _{s i} ϕ _{F}}{q N _{A}}

Depletion width at the onset of strong inversion ( $ϕ_{s} = 2 ϕ_{F}$ ), uniform doping, depletion approximation. In equilibrium (slow gate sweep), it barely grows beyond this, because the inversion charge supports any further gate charge. Under a fast ramp (deep depletion) it can exceed $W_{d m}$ .

DEPLETION CHARGE AT THRESHOLD

Q_{d, ma x} = - q N_{A} W_{d m} = - 4 ε_{s i} q N_{A} ϕ_{F}

Charge per unit area of the ionised acceptors in the depletion layer at $ϕ_{s} = 2 ϕ_{F}$ and $V_{S B} = 0$ . It is negative for a p-type body.

EXAM TIP

The criterion $ϕ_{s} = 2 ϕ_{F}$ is a convention for where the inversion layer becomes significant, not a sharp switch. The electron density at the surface keeps rising smoothly through weak inversion, and that weak-inversion charge is what carries the subthreshold current of a MOSFET.

Threshold Voltage

The threshold voltage is the gate voltage at which the surface reaches strong inversion ( $ϕ_{s} = 2 ϕ_{F}$ ). It is the sum of three pieces: the flat-band voltage, the band bending $2 ϕ_{F}$ in the silicon, and the voltage across the oxide needed to hold the depletion charge present at that point. An NMOS with $V_{T H} > 0$ has no channel at $V_{GS} = 0$ (enhancement mode). One with $V_{T H} < 0$ already has a channel at $V_{GS} = 0$ (depletion mode).

THRESHOLD VOLTAGE (NMOS, P-TYPE BODY, $V_{SB}=0$)

V_{T H 0} = V_{F B} + 2 ϕ_{F} + \frac{4 ε _{s i} q N _{A} ϕ _{F}}{C _{o x}}

Uniform body doping, with $Q_{o x}$ included through $V_{F B}$ . Equivalently $V_{T H 0} = V_{F B} + 2 ϕ_{F} + ∣ Q_{d, ma x} ∣/ C_{o x}$ .

THRESHOLD VOLTAGE (PMOS, N-TYPE BODY, $V_{BS}=0$)

V_{T H 0} = V_{F B} - 2∣ ϕ_{F} ∣ - \frac{4 ε _{s i} q N _{D} ∣ ϕ _{F} ∣}{C _{o x}}

$∣ ϕ_{F} ∣ = V_{T} ln (N_{D} / n_{i})$ . The depletion charge is positive (ionised donors) and the inversion layer is made of holes, so both terms add negatively. $V_{F B}$ uses $ϕ_{m s}$ for the n-type body.

BODY EFFECT (NMOS)

V_{T H} = V_{T H 0} + γ (2 ϕ_{F} + V_{S B} - 2 ϕ_{F}), γ = \frac{2 ε _{s i} q N _{A}}{C _{o x}}

$V_{S B} \geq 0$ is the source-to-body reverse bias, and $γ$ is the body-effect coefficient (units $V$ ). A larger $V_{S B}$ widens the depletion region and raises $V_{T H}$ . So in a stack of NMOS transistors with the body grounded, an upper device (source above ground) has a higher threshold. For PMOS the same form holds with magnitudes: $∣ V_{T H} ∣$ grows with $V_{B S} \geq 0$ , with $N_{D}$ and $∣ ϕ_{F} ∣$ in place of $N_{A}$ and $ϕ_{F}$ .

THRESHOLD-ADJUST IMPLANT

Δ V_{T H} = \frac{q D _{I}}{C _{o x}}

$D_{I}$ is the implanted dose (ions/cm $^{2}$ ), assumed to sit as a thin sheet at the Si surface. An acceptor implant into an NMOS channel raises $V_{T H}$ , and a donor implant lowers it.

INVERSION CHARGE ABOVE THRESHOLD

Q_{n} = - C_{o x} (V_{GS} - V_{T H})

Charge-sheet approximation, per unit area, for $V_{GS} > V_{T H}$ with $V_{D S} = 0$ (uniform channel). With $V_{D S} > 0$ the local channel voltage is subtracted from $V_{GS}$ , which is where the square-law I-V model comes from.

WORKED EXAMPLE · THRESHOLD, IMPLANT AND BODY EFFECT

An NMOS has $N_{A} = 1 0^{16} cm^{- 3}$ , $t_{o x} = 10 nm$ and $V_{F B} = - 0.90 V$ (conventions as above). (a) Find $V_{T H 0}$ . (b) What acceptor implant dose gives $V_{T H 0} = + 0.40 V$ ? (c) With the implant (a thin surface sheet, so $γ$ is unchanged), find $V_{T H}$ at $V_{S B} = 2 V$ .

Solution

$C_{o x} = 3.9 \times 8.85 \times 1 0^{- 14} / (1 0^{- 6}) = 3.45 \times 1 0^{- 7} F/cm^{2}$ .
$ϕ_{F} = 0.0259 ln (1 0^{16} /1.5 \times 1 0^{10}) = 0.0259 \times 13.41 = 0.347 V$ , so $2 ϕ_{F} = 0.695 V$ .
$4 ε_{s i} q N_{A} ϕ_{F} = 4 (1.035 \times 1 0^{- 12}) (1.6 \times 1 0^{- 19}) (1 0^{16}) (0.347) = 4.80 \times 1 0^{- 8} C/cm^{2}$ ; dividing by $C_{o x}$ gives $0.139 V$ .
(a) $V_{T H 0} = - 0.90 + 0.695 + 0.139 = - 0.066 V$ . It is negative, so without an implant this device is depletion mode.
(b) $Δ V_{T H} = 0.40 - (- 0.066) = 0.466 V$ , so $D_{I} = Δ V_{T H} C_{o x} / q = 0.466 \times 3.45 \times 1 0^{- 7} /1.6 \times 1 0^{- 19} \approx 1.0 \times 1 0^{12} cm^{- 2}$ .
(c) $γ = 2 ε_{s i} q N_{A} / C_{o x} = 4.07 \times 1 0^{- 8} /3.45 \times 1 0^{- 7} = 0.167 V$ . $Δ V_{T H} = 0.167 (2.695 - 0.695) = 0.167 (1.642 - 0.833) = 0.135 V$ , so $V_{T H} = 0.40 + 0.135 = 0.535 V$ .

Answer: (a) about $- 0.066 V$ ; (b) about $1.0 \times 1 0^{12} cm^{- 2}$ ; (c) about $0.535 V$

C-V Characteristics of the MOS Capacitor

Sweeping the DC gate voltage slowly while measuring the small-signal capacitance gives a curve whose shape depends on the test frequency. Majority carriers respond almost instantly. Minority carriers, which form the inversion layer, must be thermally generated in an isolated capacitor, and generation is slow.

Accumulation ( $V_{G}$ well below $V_{F B}$ ): holes screen the surface at any test frequency, so $C \approx C_{o x}$ (the maximum).
Depletion: $C$ is $C_{o x}$ in series with the depletion capacitance $C_{d e p} = ε_{s i} / W_{d}$ . As $V_{G}$ rises, $W_{d}$ widens and $C$ falls.
Strong inversion, LOW test frequency: generation and recombination keep up with the signal, the inversion layer responds, and $C$ rises back towards $C_{o x}$ .
Strong inversion, HIGH test frequency: the inversion charge cannot follow the signal, so only the depletion edge moves. $W_{d}$ is pinned at $W_{d m}$ and $C$ stays at $C_{min}$ .
Deep depletion (gate ramped faster than minority carriers can be generated): no inversion layer forms in time, $W_{d}$ grows beyond $W_{d m}$ , and $C$ falls below $C_{min}$ . This is a non-equilibrium curve, distinct from the high-frequency curve.
In a MOSFET (or any MOS structure with an adjacent n $^{+}$ region), the source and drain supply inversion electrons directly. The gate capacitance in strong inversion therefore returns to about $C_{o x}$ even at high frequency. The behaviour where C stays at $C_{min}$ belongs to an isolated capacitor.

MINIMUM (HIGH-FREQUENCY INVERSION) CAPACITANCE

\frac{1}{C _{min}} = \frac{1}{C _{o x}} + \frac{W _{d m}}{ε _{s i}}

Isolated MOS capacitor, high test frequency, equilibrium (slow) DC sweep. $W_{d m}$ is the maximum depletion width at $ϕ_{s} = 2 ϕ_{F}$ .

WORKED EXAMPLE · C_MIN FOR A GIVEN CAPACITOR

For a MOS capacitor with $N_{A} = 1 0^{16} cm^{- 3}$ and $t_{o x} = 10 nm$ ( $C_{o x} = 3.45 \times 1 0^{- 7} F/cm^{2}$ , $ϕ_{F} = 0.347 V$ ), find $C_{min} / C_{o x}$ .

Solution

$W_{d m} = 4 ε_{s i} ϕ_{F} / (q N_{A}) = 4 (1.035 \times 1 0^{- 12}) (0.347) / (1.6 \times 1 0^{- 19} \times 1 0^{16}) = 3.00 \times 1 0^{- 5} cm = 0.30 μ m$ .
$C_{d e p} = ε_{s i} / W_{d m} = 1.035 \times 1 0^{- 12} /3.00 \times 1 0^{- 5} = 3.45 \times 1 0^{- 8} F/cm^{2}$ .
$C_{min} = \frac{C _{o x} C _{d e p}}{C _{o x} + C _{d e p}} = \frac{( 3.45 \times 1 0 ^{- 7} ) ( 3.45 \times 1 0 ^{- 8} )}{3.80 \times 1 0 ^{- 7}} = 3.14 \times 1 0^{- 8} F/cm^{2}$ .

Answer: $C_{min} / C_{o x} \approx 0.091$

EXAM TIP

Even at flat band the capacitance is already below $C_{o x}$ , because the charge in the silicon spreads over a finite depth. The low- and high-frequency curves coincide in accumulation and depletion, and separate only once an inversion layer starts to form.

MOSFET I-V Characteristics: Square Law and Channel-Length Modulation

Once $V_{GS} > V_{T H}$ , an inversion channel links source and drain. The square-law model below assumes a long channel (gradual-channel approximation), constant channel mobility, no velocity saturation, and a fixed $V_{S B}$ (whose effect is carried in $V_{T H}$ ). For an n-channel device $V_{GS}$ , $V_{D S}$ and $I_{D}$ are positive. For a p-channel device, use $μ_{p}$ and the magnitudes $∣ V_{GS} ∣$ , $∣ V_{D S} ∣$ , $∣ V_{T H} ∣$ .

LINEAR (TRIODE) REGION

I_{D} = μ_{n} C_{o x} \frac{W}{L} [(V_{GS} - V_{T H}) V_{D S} - \frac{V _{D S}^{2}}{2}]

Valid for $V_{GS} > V_{T H}$ and $0 \leq V_{D S} \leq V_{GS} - V_{T H}$ . $μ_{n}$ is the electron mobility in the channel.

ON-RESISTANCE IN DEEP TRIODE

R_{o n} = \frac{1}{μ _{n} C _{o x} \frac{W}{L} ( V _{GS} - V _{T H} )}

For $V_{D S} ≪ 2 (V_{GS} - V_{T H})$ the $V_{D S}^{2}$ term is negligible, so the channel acts as a gate-controlled linear resistor.

PINCH-OFF (EDGE OF SATURATION)

V_{D S, s a t} = V_{GS} - V_{T H}

In this model the inversion charge at the drain end falls to zero at this drain voltage. The triode expression reaches its maximum here, $I_{D, s a t} = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{T H})^{2}$ .

SATURATION REGION WITH CHANNEL-LENGTH MODULATION

I_{D} = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{T H})^{2} (1 + λ V_{D S})

Valid for $V_{GS} > V_{T H}$ and $V_{D S} \geq V_{GS} - V_{T H}$ . $λ$ (1/V) models channel-length modulation: as $V_{D S}$ rises, the pinch-off point moves towards the source and the effective channel shortens. It is larger for shorter channels. With $λ = 0$ , $I_{D}$ does not depend on $V_{D S}$ in saturation.

OUTPUT RESISTANCE IN SATURATION

r_{o} = \frac{1 + λ V _{D S}}{λ I _{D}} \approx \frac{1}{λ I _{D}}

Small-signal output resistance caused by channel-length modulation. The approximation holds when $λ V_{D S} ≪ 1$ .

EXAM TIP

At $V_{D S} = V_{GS} - V_{T H}$ , the triode and saturation expressions give the same current when $λ = 0$ . If an operating point solved with the saturation formula comes out with $V_{D S} < V_{GS} - V_{T H}$ (or a triode solution comes out with $V_{D S} > V_{GS} - V_{T H}$ ), the assumed region was wrong. Redo it with the other formula.

Transconductance, Capacitances and Subthreshold Conduction

Transconductance is the change in drain current per unit change in gate voltage, and it is the key small-signal parameter of the device. Below threshold the MOSFET does not switch off abruptly: it conducts a small current that varies exponentially with gate voltage. That current sets the off-state leakage.

TRANSCONDUCTANCE IN SATURATION

g_{m} = μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{T H}) = 2 μ_{n} C_{o x} \frac{W}{L} I_{D} = \frac{2 I _{D}}{V _{GS} - V _{T H}}

Square-law model in saturation, $λ$ neglected. The three forms are equivalent; use whichever matches the given data. In the triode region, $g_{m} = μ_{n} C_{o x} (W / L) V_{D S}$ .

BODY TRANSCONDUCTANCE

g_{mb} = \frac{γ g _{m}}{2 2 ϕ _{F} + V _{S B}}

The change in $I_{D}$ per unit change of body-to-source voltage, in saturation. It follows from differentiating the body-effect expression for $V_{T H}$ .

UNITY-GAIN FREQUENCY (INTRINSIC, SATURATION)

f_{T} = \frac{g _{m}}{2 π ( C _{g s} + C _{g d} )} \approx \frac{3 μ _{n} ( V _{GS} - V _{T H} )}{4 π L ^{2}}

In saturation the intrinsic gate-source capacitance is $C_{g s} \approx \frac{2}{3} W L C_{o x}$ and the intrinsic $C_{g d} \approx 0$ . The approximate form neglects overlap and junction capacitances and uses the square-law $g_{m}$ . $f_{T}$ rises as $1/ L^{2}$ when the channel is shortened.

SUBTHRESHOLD CURRENT

I_{D} \approx I_{0} exp (\frac{V _{GS} - V _{T H}}{n V _{T}}) [1 - exp (- \frac{V _{D S}}{V _{T}})]

Valid for $V_{GS} < V_{T H}$ (weak inversion, where the current is carried by diffusion). $I_{0}$ is a device-dependent current proportional to $W / L$ . The bracket makes $I_{D}$ practically independent of $V_{D S}$ once $V_{D S}$ exceeds a few $V_{T}$ . $V_{T} = k T / q$ is the thermal voltage (25.9 mV at 300 K), not the threshold voltage.

SUBTHRESHOLD SLOPE FACTOR

n = 1 + \frac{C _{d e p}}{C _{o x}}

Neglects interface-trap capacitance (traps add a further $C_{i t} / C_{o x}$ ). $C_{d e p} = ε_{s i} / W_{d}$ is the depletion capacitance per unit area. A thinner oxide or a lighter body doping brings $n$ closer to 1.

SUBTHRESHOLD SWING

S = n V_{T} ln 10

The gate-voltage change needed for a tenfold change in subthreshold current (mV/decade). With $V_{T} = 25.9 mV$ , $V_{T} ln 10 \approx 59.6 mV$ . Since $n \geq 1$ , a conventional MOSFET at 300 K cannot switch more steeply than about 60 mV/decade. $S$ is proportional to absolute temperature.

EXAM TIP

Keep the thermal voltage $V_{T} = k T / q$ (about 25.9 mV at 300 K; it appears in subthreshold and diode equations) separate from the threshold voltage $V_{T H}$ (which appears in the square-law equations). The symbols look alike.

Scaling in MOSFETs

Scaling shrinks every lateral and vertical dimension by a factor $κ > 1$ , and two ideal rules fix what happens to voltage and doping. The table gives the multiplying factor for each quantity. It assumes the long-channel square-law model ( $I_{D} \propto C_{o x} (W / L) V^{2}$ , no velocity saturation) and that $V_{D D}$ and $V_{T H}$ scale together.

Quantity (multiplying factor)	Constant-field scaling	Constant-voltage scaling
Dimensions $L, W, t_{o x}, x_{j}$	$1/ κ$	$1/ κ$
Voltages $V_{D D}$ , $V_{T H}$	$1/ κ$	$1$ (unchanged)
Doping $N_{A}$	$κ$	$κ^{2}$
Electric field	$1$ (unchanged)	$κ$
$C_{o x}$ (per unit area)	$κ$	$κ$
Gate capacitance per device $C_{g} = C_{o x} W L$	$1/ κ$	$1/ κ$
Drain current per device $I_{D}$	$1/ κ$	$κ$
Power per device $P = I_{D} V_{D D}$	$1/ κ^{2}$	$κ$
Area per device	$1/ κ^{2}$	$1/ κ^{2}$
Device density	$κ^{2}$	$κ^{2}$
Power density (power/area)	$1$ (unchanged)	$κ^{3}$
Gate delay $τ = C_{g} V_{D D} / I_{D}$	$1/ κ$	$1/ κ^{2}$
Switching energy $C_{g} V_{D D}^{2}$ (power-delay product)	$1/ κ^{3}$	$1/ κ$

Constant-field scaling keeps the internal electric field fixed, so breakdown and hot-carrier stress do not get worse, but it requires cutting the supply and threshold voltages by $κ$ at every step. Constant-voltage scaling keeps $V_{D D}$ fixed, but the internal field rises by $κ$ and the power density by $κ^{3}$ . Reducing the supply by a factor smaller than $κ$ gives values between the two columns. Lowering $V_{T H}$ has its own limit: the subthreshold swing $S$ does not scale down with the device, so each reduction of $V_{T H}$ by $S$ raises the off-state current $I_{D} (V_{GS} = 0)$ about tenfold.

Velocity saturation: at high lateral field the carrier drift velocity saturates (about $1 0^{7} cm/s$ for electrons in Si at 300 K). The saturation current then grows roughly linearly rather than quadratically with $V_{GS} - V_{T H}$ , and the square-law model overestimates $I_{D}$ .
Threshold roll-off: as $L$ shrinks, the source and drain depletion regions account for a larger share of the depletion charge under the gate, so $V_{T H}$ falls as $L$ decreases.
Drain-induced barrier lowering (DIBL): in a short channel, raising $V_{D S}$ lowers the source-to-channel barrier, so $V_{T H}$ falls as $V_{D S}$ rises and the output resistance drops.
Punch-through: if the source and drain depletion regions merge, current flows below the surface, largely outside the gate's control.
Hot carriers: high fields near the drain can inject carriers into the oxide and shift $V_{T H}$ over time. This is the reliability concern that constant-field scaling avoids.
Gate tunnelling: a very thin oxide allows direct tunnelling current through the gate, which limits how far $t_{o x}$ can be reduced.

EXAM TIP

To re-derive any scaling factor, substitute the rules for dimensions, voltage and doping into $C_{o x} \propto 1/ t_{o x}$ and $I_{D} \propto C_{o x} (W / L) V^{2}$ . Then power is $P = I_{D} V$ , area scales as $1/ κ^{2}$ , and delay is $τ = C_{g} V / I_{D}$ with $C_{g} = C_{o x} W L$ .

PREVIOUS-YEAR QUESTIONS

7 questions from the EC papers

Try each question first, then open the answer. We placed each question under a topic ourselves; the exam paper does not label topics.

See these papers in full: GATE ECE 2024 · GATE ECE 2023 · GATE ECE 2022 · GATE ECE 2020

GATE 2024 EC Q.61

GATE 2024 · ECQ.61 · 2 marks · NAT

Consider a MOS capacitor made with p-type silicon. It has an oxide thickness of 100 nm, a fixed positive oxide charge of $1 0^{- 8} C/cm^{2}$ at the oxide-silicon interface, and a metal work function of 4.6 eV. Assume that the relative permittivity of the oxide is 4 and the absolute permittivity of free space is $8.85 \times 1 0^{- 14} F/cm$ . If the flatband voltage is 0 V, the work function of the p-type silicon (in eV, rounded off to two decimal places) is ______.

Answer and solution

GATE 2024 EC Q.61: answer and solution

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GATE 2024 EC Q.61: answer and solution

GATE 2024 EC Q.64

GATE 2024 · ECQ.64 · 2 marks · NAT

An NMOS transistor operating in the linear region has $I_{D S}$ of 5 μA at $V_{D S}$ of 0.1 V. Keeping $V_{GS}$ constant, the $V_{D S}$ is increased to 1.5 V. Given that $μ_{n} C_{o x} \frac{W}{L} = 50 μ A/V^{2}$ , the transconductance at the new operating point (in μA/V, rounded off to two decimal places) is ____.

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GATE 2024 EC Q.64: answer and solution

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GATE 2024 EC Q.64: answer and solution

GATE 2023 EC Q.19

GATE 2023 · ECQ.19 · 1 mark · MCQ

For a MOS capacitor, $V_{f b}$ and $V_{t}$ are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width ( $W_{d e p}$ ) for varying gate voltage ( $V_{g}$ ) is best represented by

GATE 2023 EC question 19: Four candidate plots of W_dep (y-axis) vs V_g (x-axis), each x-axis marked with two ticks V_fb (left) and V_t (right), and… — Figure from the GATE 2023 EC paper. It is part of the question.

(A)
Figure — Wdep rises before Vfb and saturates to a plateau before Vt is reached (early saturation, offset from the marked voltages)
(B)
Figure — Wdep = 0 for Vg < Vfb, rises smoothly starting exactly at Vfb, and saturates to a constant plateau at Vg = Vt, remaining flat through inversion
(C)
Figure — Wdep starts at a constant nonzero value through accumulation and depletion, then decreases to zero at Vt and stays zero in inversion
(D)
Figure — Wdep = 0 in accumulation and inversion, rising to a single peak only inside the depletion region between Vfb and Vt (arch shape)

Answer and solution

GATE 2023 EC Q.19: answer and solution

GATE 2022 EC Q.20

GATE 2022 · ECQ.20 · 1 mark · MCQ

The ideal long channel $n$ MOSFET and $p$ MOSFET devices shown in the circuits have threshold voltages of 1 V and $- 1$ V, respectively. The MOSFET substrates are connected to their respective sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ____________.

GATE 2022 EC question 20: Two separate circuits side by side. — Figure from the GATE 2022 EC paper. It is part of the question.

(A)
V1 = 5 V, V2 = 5 V
(B)
V1 = 5 V, V2 = 4 V
(C)
V1 = 4 V, V2 = 5 V
(D)
V1 = 4 V, V2 = -5 V

Answer and solution

GATE 2022 EC Q.20: answer and solution

GATE 2022 EC Q.34

GATE 2022 · ECQ.34 · 1 mark · NAT

An ideal MOS capacitor (p-type semiconductor) is shown in the figure. The MOS capacitor is under strong inversion with $V_{G} = 2$ V. The corresponding inversion charge density ( $Q_{I N}$ ) is $2.2 μ C / cm^{2}$ . Assume oxide capacitance per unit area as $C_{O X} = 1.7 μ F / cm^{2}$ . For $V_{G} = 4$ V, the value of $Q_{I N}$ is ______ $μ C / cm^{2}$ (rounded off to one decimal place).

GATE 2022 EC question 34: Cross-section of an ideal MOS capacitor: from left to right, a thin black rectangular 'Metal' gate electrode, then a thin… — Figure from the GATE 2022 EC paper. It is part of the question.

Answer and solution

GATE 2022 EC Q.34: answer and solution

GATE 2022 EC Q.40

GATE 2022 · ECQ.40 · 2 marks · MCQ

Consider an ideal long channel nMOSFET (enhancement-mode) with gate length 10 μm and width 100 μm. The product of electron mobility (μₙ) and oxide capacitance per unit area (C_OX) is μₙC_OX = 1 mA/V². The threshold voltage of the transistor is 1 V. For a gate-to-source voltage V_GS = [2 − sin(2t)] V and drain-to-source voltage V_DS = 1 V (substrate connected to the source), the maximum value of the drain-to-source current is ______.

(A)
40 mA
(B)
20 mA
(C)
15 mA
(D)
5 mA

Answer and solution

GATE 2022 EC Q.40: answer and solution

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GATE 2022 EC Q.40: answer and solution

GATE 2020 EC Q.32

GATE 2020 · ECQ.32 · 2 marks · MCQ

The band diagram of a p-type semiconductor with a band-gap of 1 eV is shown. Using this semiconductor, a MOS capacitor having $V_{T H}$ of $- 0.16 V$ , $C_{o x}^{'}$ of $100 nF/cm^{2}$ and a metal work function of $3.87 eV$ is fabricated. There is no charge within the oxide. If the voltage across the capacitor is $V_{T H}$ , the magnitude of depletion charge per unit area (in $C/cm^{2}$ ) is

GATE 2020 EC question 32: Energy band diagram of a p-type semiconductor, vertical energy axis. — Figure from the GATE 2020 EC paper. It is part of the question.

(A)
1.70 x 10^-8
(B)
0.52 x 10^-8
(C)
1.41 x 10^-8
(D)
0.93 x 10^-8

Answer and solution

GATE 2020 EC Q.32: answer and solution

PRACTICE

5 questions to test yourself

PRACTICE 11 mark · MCQ

An NMOS capacitor (gate on p-type Si) has zero effective oxide charge ( $Q_{o x} = 0$ ) and a gate work function equal to the semiconductor work function. What is the flat-band voltage $V_{F B}$ ?

(A)
0 V
(B)
Equal to $2 ϕ_{F}$
(C)
Equal to $V_{T H}$
(D)
Cannot be determined without $N_{A}$

Answer and solution

Answer: (A)

Flat-band voltage: $V_{F B} = ϕ_{m s} - \frac{Q _{o x}}{C _{o x}}$ .
Equal work functions give $ϕ_{m s} = ϕ_{m} - ϕ_{se mi co n d u c t or} = 0$ , and $Q_{o x} = 0$ is given.
Both terms vanish, so $V_{F B} = 0 V$ .

PRACTICE 22 marks · NAT

An NMOS device has p-type body doping $N_{A} = 5 \times 1 0^{15} cm^{- 3}$ , oxide thickness $t_{o x} = 20 nm$ , flat-band voltage $V_{F B} = - 0.30 V$ and $V_{S B} = 0$ . Take $n_{i} = 1.5 \times 1 0^{10} cm^{- 3}$ at 300 K, $ε_{o x} = 3.9 ε_{0}$ , $ε_{s i} = 11.7 ε_{0}$ , $ε_{0} = 8.85 \times 1 0^{- 14} F/cm$ , $q = 1.6 \times 1 0^{- 19} C$ and $k T / q = 25.9 mV$ . Find the threshold voltage $V_{T H}$ in volts.

Answer and solution

Answer: $0.55$ (accepted range $\pm 0.02$ )

$C_{o x} = ε_{o x} / t_{o x} = (3.9) (8.85 \times 1 0^{- 14}) / (2 \times 1 0^{- 6}) = 1.726 \times 1 0^{- 7} F/cm^{2}$ .
$ϕ_{F} = (k T / q) ln (N_{A} / n_{i}) = 0.0259 ln (3.33 \times 1 0^{5}) = 0.0259 \times 12.72 = 0.329 V$ , so $2 ϕ_{F} = 0.659 V$ .
$ε_{s i} = 11.7 \times 8.85 \times 1 0^{- 14} = 1.035 \times 1 0^{- 12} F/cm$ . $4 ε_{s i} q N_{A} ϕ_{F} = 4 (1.035 \times 1 0^{- 12}) (1.6 \times 1 0^{- 19}) (5 \times 1 0^{15}) (0.329) = 3.30 \times 1 0^{- 8} C/cm^{2}$ . Dividing by $C_{o x}$ gives $0.191 V$ .
$V_{T H} = V_{F B} + 2 ϕ_{F} + \frac{4 ε _{s i} q N _{A} ϕ _{F}}{C _{o x}} = - 0.30 + 0.659 + 0.191 = 0.55 V$ .

PRACTICE 31 mark · MSQ

An ideal MOS capacitor is made on p-type silicon, with no source or drain regions. Its C-V curve is measured with a slow DC gate-voltage sweep, once with a low-frequency and once with a high-frequency small-signal test voltage. Which of the following statements are correct?

(A)
At low frequency, C rises back to nearly $C_{o x}$ in strong inversion
(B)
At high frequency, C stays near its minimum value in strong inversion
(C)
At high frequency, C also rises back to $C_{o x}$ in strong inversion
(D)
In accumulation, C is approximately $C_{o x}$ at both low and high frequency

Answer and solution

Answer: (A), (B), (D)

In strong inversion at low test frequency, minority carriers (electrons) are generated fast enough to follow the signal, so the inversion layer responds and C rises back towards $C_{o x}$ . (A) is correct.
At high test frequency, generation is too slow for the inversion charge to follow the signal, and no source or drain region can supply electrons. Only the depletion edge at $W_{d m}$ responds, so C stays at $C_{min}$ ( $C_{o x}$ in series with $ε_{s i} / W_{d m}$ ). (B) is correct and (C) is incorrect.
In accumulation, majority carriers (holes) respond at both frequencies, so $C \approx C_{o x}$ in both cases. (D) is correct.

PRACTICE 41 mark · NAT

A long-channel NMOS transistor is biased in saturation with overdrive voltage $V_{GS} - V_{T H} = 0.5 V$ and $μ_{n} C_{o x} (W / L) = 200 μ A/V^{2}$ . Neglecting channel-length modulation, find the transconductance $g_{m}$ in $μ A/V$ .

Answer and solution

Answer: $100$ (accepted range $\pm 1$ )

In saturation, $I_{D} = \frac{1}{2} μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{T H})^{2}$ .
$g_{m} = \frac{\partial I _{D}}{\partial V _{GS}} = μ_{n} C_{o x} \frac{W}{L} (V_{GS} - V_{T H})$ .
$g_{m} = 200 \times 0.5 = 100 μ A/V$ . Check: $I_{D} = \frac{1}{2} (200) (0.25) = 25 μ A$ , and $2 I_{D} / (V_{GS} - V_{T H}) = 50/0.5 = 100 μ A/V$ .

PRACTICE 52 marks · MCQ

Under ideal constant-field scaling by a factor $κ > 1$ (all dimensions, the supply voltage and the threshold voltage scaled by $1/ κ$ ; doping scaled by $κ$ ; long-channel square-law behaviour), how does the power density (power per unit chip area) change?

(A)
Stays constant
(B)
Increases by a factor of $κ$
(C)
Increases by a factor of $κ^{2}$
(D)
Decreases by a factor of $κ$

Answer and solution

Answer: (A)

Constant-field scaling: $L, W, t_{o x} \to (\cdot) / κ$ ; $V_{D D}, V_{T H} \to (\cdot) / κ$ ; $N_{A} \to κ N_{A}$ . The internal electric fields stay the same.
Current per device: $I_{D} \propto C_{o x} (W / L) V^{2}$ . Here $C_{o x} \propto κ$ , $W / L$ is unchanged and $V^{2} \propto 1/ κ^{2}$ , so $I_{D} \to I_{D} / κ$ .
Power per device: $P = I V \to (I / κ) (V / κ) = P / κ^{2}$ .
Area per device shrinks as $1/ κ^{2}$ , so power density $\to (P / κ^{2}) / (A / κ^{2}) = P / A$ . It is unchanged.

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GATE EC

MOS capacitor, MOSFET, scaling in MOSFETs

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